ZHCSCE2I October 2013 – March 2022 BQ76920 , BQ76930 , BQ76940
PRODMIX
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
7.6 Timing Requirements
| I2C COMPATIBLE INTERFACE | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|
| VIL | Input low logic threshold | REGOUT x 0.25 | V | ||
| VIH | Input high logic threshold | REGOUT x 0.75 | V | ||
| VOL | Output low logic drive | 0.20 | V | ||
| tf | SCL, SDA fall time | 0.40 | |||
| VOH | Output high logic drive (not applicable due to open-drain outputs) | N/A | N/A | V | |
| tHIGH | SCL pulse width high | 4.0 | μs | ||
| tLOW | SCL pulse width low | 4.7 | μs | ||
| tSU;STA | Setup time for START condition | 4.7 | μs | ||
| tHD;STA | START condition hold time after which first clock pulse is generated | 4.0 | μs | ||
| tSU;DAT | Data setup time | 250 | ns | ||
| tHD;DAT | Data hold time | 0 | μs | ||
| tSU;STO | Setup time for STOP condition | 4.0 | μs | ||
| tBUF | Time the bus must be free before new transmission can start | 4.7 | μs | ||
| tVD;DAT | Clock low to data out valid | 900 | ns | ||
| tHD;DAT | Data out hold time after clock low | 0 | ns | ||
| fSCL | Clock frequency | 0 | 100 | kHz | |
Figure 7-1 I2C Timing