ZHCSPQ2 December 2022 BQ28Z620
PRODUCTION DATA
| PARAMETER | TEST CONDITION | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tR | Clock rise time | 10% to 90% | 300 | ns | ||
| tF | Clock fall time | 90% to 10% | 300 | ns | ||
| tHIGH | Clock high period | 600 | ns | |||
| tLOW | Clock low period | 1.3 | μs | |||
| tSU(START) | Repeated start setup time | 600 | ns | |||
| td(START) | Start for first falling edge to SCL | 600 | ns | |||
| tSU(DATA) | Data setup time | 100 | ns | |||
| tHD(DATA) | Data hold time | 0 | μs | |||
| tSU(STOP) | Stop setup time | 600 | ns | |||
| tBUF | Bus free time between stop and start | 1.3 | μs | |||
| fSW | Clock operating frequency | SLAVE mode, SCL 50% duty cycle | 400 | kHz | ||
Figure 8-1 I2C Timing