ZHCSG50B March 2016 – March 2017
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Functional Block Diagram
- 9.2
Feature Description
- 9.2.1 Device Power-On-Reset (POR)
- 9.2.2 Device Power Up from Battery without Input Source
- 9.2.3 Device Power Up from Input Source
- 9.2.4 Input Current Optimizer (ICO)
- 9.2.5 Boost Mode Operation from Battery
- 9.2.6 Power Path Management
- 9.2.7 Battery Charging Management
- 9.2.8 Battery Monitor
- 9.2.9 Status Outputs (PG, STAT, and INT)
- 9.2.10 BATFET (Q4) Control
- 9.2.11 Current Pulse Control Protocol
- 9.2.12 Input Current Limit on ILIM
- 9.2.13 Thermal Regulation and Thermal Shutdown
- 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
- 9.2.15 Battery Protection
- 9.2.16 Serial Interface
- 9.3 Device Functional Modes
- 9.4 Register Map
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 66) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.
- Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
- Put output capacitor near to the inductor and the IC.
- Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
- Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
- Connect all grounds together to reduce PCB size and improve thermal dissipation.
- Avoid ground planes in parallel with high frequency traces in other layers.
12.2 Layout Example
Figure 66. High Frequency Current Path