ZHCSE45C July 2015 – May 2018
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description | |
|---|---|---|---|---|---|
| 7 | CONV_START | R/W | by REG_RST
by Watchdog |
ADC Conversion Start Control
0 – ADC conversion not active (default). 1 – Start ADC Conversion This bit is read-only when CONV_RATE = 1. The bit stays high during ADC conversion and during input source detection. |
|
| 6 | CONV_RATE | R/W | by REG_RST
by Watchdog |
ADC Conversion Rate Selection
0 – One shot ADC conversion (default) 1 – Start 1s Continuous Conversion |
|
| 5 | BOOST_FREQ | R/W | by REG_RST
by Watchdog |
Boost Mode Frequency Selection
0 – 1.5MHz (default) 1 – 500KHz Note: Write to this bit is ignored when OTG_CONFIG is enabled. |
|
| 4 | ICO_EN | R/W | by REG_RST | Input Current Optimizer (ICO) Enable
0 – Disable ICO Algorithm 1 – Enable ICO Algorithm (default) |
|
| 3 | Reserved | R/W | by REG_RST | Reserved (default = 0) | |
| 2 | Reserved | R/W | by REG_RST | Reserved (default = 0) | |
| 1 | FORCE_DPDM | R/W | by REG_RST
by Watchdog |
Force Input Detection
0 – Not in PSEL detection (default) 1 – Force PSEL detection |
|
| 0 | AUTO_DPDM_EN | R/W | by REG_RST | Automatic Input Detection Enable
0 –Disable PSEL detection when VBUS is plugged-in 1 –Enable PEL detection when VBUS is plugged-in (default) |
|