ZHCSE45C July 2015 – May 2018
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Functional Block Diagram
- 9.2
Feature Description
- 9.2.1 Device Power-On-Reset (POR)
- 9.2.2 Device Power Up from Battery without Input Source
- 9.2.3 Device Power Up from Input Source
- 9.2.4 Input Current Optimizer (ICO)
- 9.2.5 Boost Mode Operation from Battery
- 9.2.6 Power Path Management
- 9.2.7 Battery Charging Management
- 9.2.8 Battery Monitor
- 9.2.9 Status Outputs (PG, STAT, and INT)
- 9.2.10 BATET (Q4) Control
- 9.2.11 Current Pulse Control Protocol
- 9.2.12 Input Current Limit on ILIM
- 9.2.13 Thermal Regulation and Thermal Shutdown
- 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
- 9.2.15 Battery Protection
- 9.2.16 Serial Interface
- 9.3 Device Functional Modes
- 9.4 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9.2.6.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5 V).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET. The status register VSYS_STAT bit goes high when the system is in minimum system voltage regulation.
Figure 9. V(SYS) vs V(BAT)