ZHCSDI5C March 2015 – October 2022 BQ25895
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description | |
|---|---|---|---|---|---|
| 7 | CONV_START | R/W | by REG_RST by Watchdog | ADC Conversion Start Control 0 – ADC conversion not active (default). 1 – Start ADC Conversion This bit is read-only when CONV_RATE = 1. The bit stays high during ADC conversion and during input source detection. | |
| 6 | CONV_RATE | R/W | by REG_RST by Watchdog | ADC Conversion Rate Selection 0 – One shot ADC conversion (default) 1 – Start 1s Continuous Conversion | |
| 5 | BOOST_FREQ | R/W | by REG_RST by Watchdog | Boost Mode Frequency Selection 0 – 1.5MHz 1 – 500KHz (default) Note: Write to this bit is ignored when OTG_CONFIG is enabled. | |
| 4 | ICO_EN | R/W | by REG_RST | Input Current Optimizer (ICO) Enable 0 – Disable ICO Algorithm 1 – Enable ICO Algorithm (default) | |
| 3 | HVDCP_EN | R/W | by REG_RST | High Voltage DCP Enable 0 – Disable HVDCP handshake 1 – Enable HVDCP handshake (default) | |
| 2 | MAXC_EN | R/W | by REG_RST | MaxCharge Adapter Enable 0 – Disable MaxCharge handshake 1 – Enable MaxCharge handshake (default) | |
| 1 | FORCE_DPDM | R/W | by REG_RST by Watchdog | Force D+/D- Detection 0 – Not in D+/D- or PSEL detection (default) 1 – Force D+/D- detection | |
| 0 | AUTO_DPDM_EN | R/W | by REG_RST | Automatic D+/D- Detection Enable 0 –Disable D+/D- or PSEL detection when VBUS is plugged-in 1 –Enable D+/D- or PEL detection when VBUS is plugged-in (default) | |