ZHCSJR3B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Device Power-On-Reset
- 8.3.2 Device Power Up from Input Source
- 8.3.3 Input Current Optimizer (ICO)
- 8.3.4 Battery Charging Management
- 8.3.5 Integrated 16-Bit ADC for Monitoring
- 8.3.6 Status Outputs
- 8.3.7 Input Current Limit on ILIM Pin
- 8.3.8 Voltage and Current Monitoring
- 8.3.9 Thermal Regulation and Thermal Shutdown
- 8.3.10 Battery Protection
- 8.3.11 Serial Interface
- 8.4 Device Functional Modes
- 8.5
Register Maps
- 8.5.1 Cell Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
- 8.5.2 Charger Current Limit Register (Address = 01h) [reset = 5Eh]
- 8.5.3 Input Voltage Limit Register (Address = 02h) [reset = 84h]
- 8.5.4 Input Current Limit Register (Address = 03h) [reset = 39h ]
- 8.5.5 Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
- 8.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Dh]
- 8.5.7 Charger Control 2 Register (Address = 06h) [reset = 7Dh]
- 8.5.8 Charger Control 3 Register (Address = 07h) [reset = 00h]
- 8.5.9 Charger Control 4 Register (Address = 08h) [reset = 0Dh]
- 8.5.10 Reserved Register (Address = 09h) [reset = 00h]
- 8.5.11 ICO Current Limit in Use Register (Address = 0Ah) [reset = XXh]
- 8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
- 8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
- 8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
- 8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
- 8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
- 8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
- 8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
- 8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
- 8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
- 8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
- 8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
- 8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
- 8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
- 8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
- 8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
- 8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
- 8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
- 8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
- 8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
- 8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
- 8.5.32 VCELLTOP ADC 1 Register (Address = 1Fh) [reset = 00h]
- 8.5.33 VCELLTOP ADC 0 Register (Address = 20h) [reset = 00h]
- 8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
- 8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
- 8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
- 8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
- 8.5.38 Part Information Register (Address = 25h) [reset = 28h]
- 8.5.39 VCELLBOT ADC 1 Register (Address = 26h) [reset = 00h]
- 8.5.40 VCELLBOT ADC 0 Register (Address = 27h) [reset = 00h]
- 8.5.41 Cell Balancing Control 1 Register (Address = 28h) [reset = 2Ah]
- 8.5.42 Cell Balancing Control 2 Register (Address = 29h) [reset = F4h]
- 8.5.43 Cell Balancing Status and Control Register (Address = 2Ah) [reset = 81h]
- 8.5.44 Cell Balancing Flag Register (Address = 2Bh) [reset = 00h]
- 8.5.45 Cell Balancing Mask Register (Address = 2Ch) [reset = 00h]
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.4.1 Host Mode and Default Mode
The BQ2588x is a host controlled charger, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WD_STAT bit is HIGH. When the charger is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the registers are in the default settings. During default mode, any change on PSEL pin will make real time internal reference change.
In default mode, the device keeps charging the battery with default 12-hour fast charging safety timer.
A I2C write to the registers transitions the charger from default mode to host mode and watchdog timer is reset. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer (WD_STAT bit = 1) is expired, the device returns to default mode and all registers are reset to default values except as detailed in the Register Maps section. The Watchdog timer will be reset on any write if the watchdog timer has expired.
Figure 23. Watchdog Timer Flow Chart