ZHCSJ56C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Device Power-On-Reset
- 8.3.2 Device Power Up from Battery without Input Source
- 8.3.3 Device Power Up from Input Source
- 8.3.4 Input Current Optimizer (ICO)
- 8.3.5 Buck Mode Operation from Battery (OTG)
- 8.3.6 Power Path Management
- 8.3.7 Battery Charging Management
- 8.3.8 Integrated 16-Bit ADC for Monitoring
- 8.3.9 Status Outputs (PG, and INT)
- 8.3.10 Input Current Limit on ILIM Pin
- 8.3.11 Voltage and Current Monitoring
- 8.3.12 Thermal Regulation and Thermal Shutdown
- 8.3.13 Battery Protection
- 8.3.14 Serial Interface
- 8.4 Device Functional Modes
- 8.5
Register Maps
- 8.5.1 Battery Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
- 8.5.2 Charger Current Limit Register (Address = 01h) [reset = 54h]
- 8.5.3 Input Voltage Limit Register (Address = 02h) [reset = 85h]
- 8.5.4 Input Current Limit Register (Address = 03h) [reset = 39h]
- 8.5.5 Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
- 8.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Dh]
- 8.5.7 Charger Control 2 Register (Address = 06h) [reset = 7Dh]
- 8.5.8 Charger Control 3 Register (Address = 07h) [reset = 0Ah]
- 8.5.9 Charger Control 4 Register (Address = 08h) [reset = 0Dh]
- 8.5.10 OTG Control Register (Address = 09h) [reset = F6h]
- 8.5.11 ICO Current Limit Register (Address = 0Ah) [reset = XXh]
- 8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
- 8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
- 8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
- 8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
- 8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
- 8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
- 8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
- 8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
- 8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
- 8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
- 8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
- 8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
- 8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
- 8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
- 8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
- 8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
- 8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
- 8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
- 8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
- 8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
- 8.5.32 VSYS ADC 1 Register (Address = 1Fh) [reset = 00h]
- 8.5.33 VSYS ADC 0 Register (Address = 20h) [reset = 00h]
- 8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
- 8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
- 8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
- 8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
- 8.5.38 Part Information Register (Address = 25h) [reset = 11h]
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
YFF (I2C controlled)
25-Pin DSBGA
Top View
Top View = Xray through a soldered down part with A1 starting in upper left corner
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BAT | C4 | P | Battery Power Connection – The internal BATFET is connected between SYS and BAT. Connect a 10µF ceramic capacitor closely to the BAT pin and GND. |
| C5 | |||
| BATN | E4 | AI | Negative Battery Sense Terminal – Kelvin connect as close as possible to negative battery terminal |
| BATP | E5 | AI | Positive Battery Sense Terminal – Kelvin connect as close as possible to positive battery terminal |
| BTST | D5 | P | PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap diode. Connect a 0.047µF bootstrap capacitor from SW to BTST. |
| CE | E1 | DI | Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating. |
| D+ | C1 | AIO | Positive USB data line – D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and secondary detection in BC1.2. |
| D– | D1 | AIO | Negative USB data line – D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and secondary detection in BC1.2. |
| GND | A3 | — | Ground Return |
| B3 | |||
| ILIM | D3 | AI | Input Current Limit – ILIM pin sets the maximum input current and can be used to monitor input current. IINDPM loop regulates ILIM pin voltage at 0.8 V. When ILIM pin is less than 0.8 V, the input current limit can be calculated by IIN = KILIM x VILIM / (RILIM x 0.8 V). A resistor connected from ILIM pin to ground sets the current limit as IINMAX = KILIM / RILIM. The actual input current limit is the lower limit set by ILIM pin (when EN_ILIM bit is HIGH) or IINDPM register bits. Input current limit less than 500mA is not supported on ILIM pin. The ILIM pin function can be disabled when EN_ILIM bit is 0. |
| INT | C3 | DO | Open Drain Active Low Interrupt Output – Connect /INT to the logic rail via a 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to the host to report charger device status and fault. |
| PG | C2 | DO | Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if the input voltage is within VVBUS_OP, and can provide more than IPOORSRC. |
| PMID | A2 | P | Blocking MOSFET Connection – Given the total input capacitance, place 1µF on VBUS, and the rest on PMID, as close to the IC as possible. Typical value: 10µF ceramic capacitor |
| B2 | |||
| REGN | D4 | P | Gate Drive Supply – Bias supply for internal MOSFETs driver and IC. Bypass REGN to GND with a 4.7µF ceramic capacitor. |
| SCL | D2 | DI | I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor. |
| SDA | E2 | DIO | I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor. |
| SW | A4 | P | Inductor Connection – Connect to the switched side of the external inductor. |
| A5 | |||
| SYS | B4 | P | System Connection – The internal BATFET is connected between SYS and BAT. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 44µF ceramic capacitor closely to the SYS pin and GND.
|
| B5 | |||
| TS | E3 | AI | Temperature Qualification Voltage – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin is out of range. Recommend 103AT-2 thermistor. |
| VBUS | A1 | P | Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1µF ceramic capacitor, placed as close to the IC as possible. |
| B1 | |||