ZHCSGD8A May 2017 – May 2018
PRODUCTION DATA.
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC is disabled in low power mode. When enabling ADC, the device exit low power mode at battery only.
| I2C
3Bh |
FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | ADC_CONV | R/W | 0b | Typical ADC conversion time is 10 ms.
0b: One-shot update. Do one set of conversion updates to registers REG0x27/26(), REG0x29/28(), REG0x2B/2A(), and REG0x2D/2C() after ADC_START = 1. 1b: Continuous update. Do a set of conversion updates to registers REG0x27/26(), REG0x29/28(), REG0x2B/2A(), and REG0x2D/2C() every 1 sec. |
| 6 | ADC_START | R/W | 0b |
0b: No ADC conversion 1b: Start ADC conversion. After the one-shot update is complete, this bit automatically resets to zero |
| 5 | ADC_
FULLSCALE |
R/W | 1b |
ADC input voltage range. When input voltage is below 5 V, or battery is 1S, full scale 2.04 V is recommended. 0b: 2.04 V 1b: 3.06 V <default at POR> |
| 4-0 | Reserved | R/W | 00000b | Reserved |
| I2C
3Ah |
FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | EN_ADC_CMPIN | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 6 | EN_ADC_VBUS | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 5 | EN_ADC_PSYS | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 4 | EN_ADC_IIN | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 3 | EN_ADC_IDCHG | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 2 | EN_ADC_ICHG | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 1 | EN_ADC_VSYS | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |
| 0 | EN_ADC_VBAT | R/W | 0b |
0b: Disable <default at POR> 1b: Enable |