ZHCSGD8A May 2017 – May 2018
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power-Up from Battery Without DC Source
- 8.3.2 Power-Up From DC Source
- 8.3.3 USB On-The-Go (OTG)
- 8.3.4 Converter Operation
- 8.3.5 Current and Power Monitor
- 8.3.6 Input Source Dynamic Power Manage
- 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
- 8.3.8 Processor Hot Indication
- 8.3.9 Device Protection
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Map
- 8.6.1
Setting Charge and PROCHOT Options
- 8.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E20Eh]
- 8.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]
- 8.6.1.3 ChargeOption2 Register (I2C address = 33/32h) [reset = 2B7]
- 8.6.1.4 ChargeOption3 Register (I2C address = 35/34h) [reset = 0h]
- 8.6.1.5 ProchotOption0 Register (I2C address = 37/36h) [reset = 04A54h]
- 8.6.1.6 ProchotOption1 Register (I2C address = 39/38h) [reset = 8120h]
- 8.6.1.7 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
- 8.6.2 Charge and PROCHOT Status
- 8.6.3 ChargeCurrent Register (I2C address = 03/02h) [reset = 0h]
- 8.6.4 MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
- 8.6.5 MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
- 8.6.6 Input Current and Input Voltage Registers for Dynamic Power Management
- 8.6.7 OTGVoltage Register (I2C address = 07/06h) [reset = 0h]
- 8.6.8 OTGCurrent Register (I2C address = 09/08h) [reset = 0h]
- 8.6.9 ADCVBUS/PSYS Register (I2C address = 27/26h)
- 8.6.10 ADCIBAT Register (I2C address = 29/28h)
- 8.6.11 ADCIINCMPIN Register (I2C address = 2B/2Ah)
- 8.6.12 ADCVSYSVBAT Register (I2C address = 2D/2Ch)
- 8.6.13 ID Registers
- 8.6.1
Setting Charge and PROCHOT Options
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
RSN Package
32-Pin WQFN
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| ACN | 2 | PWR | Input current sense resistor negative input. The leakage on ACP and ACN are matched. The series resistors on the ACP and ACN pins are placed between sense resistor and filter cap. Refer to Application and Implementation for ACP/ACN filter design. |
| ACP | 3 | PWR | Input current sense resistor positive input. The leakage on ACP and ACN are matched. The series resistors on the ACP and ACN pins are placed between sense resistor and filter cap. Refer to Application and Implementation for ACP/ACN filter design. |
| BATDRV | 21 | O | P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on during fast charge and supplement mode. |
| BTST1 | 30 | PWR | Buck mode high side power MOSFET driver power supply. Connect a 0.047-µF capacitor between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated. |
| BTST2 | 25 | PWR | Boost mode high side power MOSFET driver power supply. Connect a 0.047-μF capacitor between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated. |
| CELL_BATPRESZ | 18 | I | Battery cell selection pin for 1–4 cell battery setting. CELL_BATPRESZ pin is biased from VDDA. CELL_BATPRESZ pin also sets SYSOVP threshold to 5 V for 1-cell, 12 V for 2-cell, and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is pulled below VCELL_BATPRESZ_FALL to indicate battery removal. The device exits LEARN mode, and disables charge. REG0x05/04() goes back to default. |
| CHRG_OK | 4 | O | Open drain active high indicator to inform the system good power source is connected to the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS is falls below 3.2 V or rises above 26 V, CHRG_OK is LOW. When fault occurs, CHRG_OK is asserted LOW. |
| CMPIN | 14 | I | Input of independent comparator. The independent comparator compares the voltage sensed on CMPIN pin to internal reference, and its output is on CMPOUT pin. Internal reference, output polarity and deglitch time is selectable by I2C. With polarity HIGH (REG0x30[6] = 1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity LOW (REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent comparator is not in use, tie CMPIN to ground. |
| CMPOUT | 15 | O | Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup supply rail. Internal reference, output polarity and deglitch time are selectable by I2C. |
| COMP2 | 17 | I | Buck boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 pin RC network. |
| COMP1 | 16 | I | Buck boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 pin RC network. |
| EN_OTG | 5 | I | Active HIGH to enable OTG mode. When EN_OTG pin is HIGH and REG0x35[4] is HIGH, OTG can be enabled, refer to USB On-The-Go (OTG) for details of how to enable OTG function |
| HIDRV1 | 31 | O | Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET gate. |
| HIDRV2 | 24 | O | Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET gate. |
| IADPT | 8 | I/O | Buffered adapter current output. V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)). With ratio selectable in REG0x00[4]. Place a resistor from the IADPT pin to ground corresponding to inductor in use. For 2.2 µH, the resistor is 137 kΩ. Place 100-pF or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V. |
| IBAT | 9 | O | Buffered battery current selected by I2C. V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) for charge current, or V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable in REG0x00[3]. Place 100-pF or less ceramic decoupling capacitor from IBAT pin to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V. |
| ILIM_HIZ | 6 | I | Input current limit input. Program ILIM_HIZ voltage by connecting a resistor divider from supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM × RAC, in which IDPM is the target input current. The input current limit used by the charger is the lower setting of ILIM_HIZ pin and REG0x0F() and REG0x0E(). When the pin voltage is below 0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is above 0.8 V, the device is out of Hi-Z mode. |
| LODRV1 | 29 | O | Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET gate. |
| LODRV2 | 26 | O | Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET gate. |
| PGND | 27 | GND | Device power ground. |
| PROCHOT | 11 | O | Active low open drain output of processor hot indicator. It monitors adapter input current, battery discharge current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is asserted. The minimum pulse width is adjustable in REG0x36[5:2]. |
| PSYS | 10 | O | Current mode system power monitor. The output current is proportional to the total power from the adapter and battery. The gain is selectable through I2C. Place a resistor from PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V. Place a capacitor in parallel with the resistor for filtering. |
| REGN | 28 | PWR | 6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power ground. REGN pin output is for power stage gate drive. |
| SCL | 13 | I | I2C clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to I2C specifications. |
| SDA | 12 | I/O | I2C open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to I2C specifications. |
| SRN | 19 | PWR | Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with optional 0.1-μF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and SRN. |
| SRP | 20 | PWR | Charge current sense resistor positive input. Connect 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and SRN. Connect SRP pin with optional 0.1-uF ceramic capacitor to GND for common-mode filtering. |
| SW1 | 32 | PWR | Buck mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. |
| SW2 | 23 | PWR | Boost mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. |
| VBUS | 1 | PWR | Charger input voltage. An input low pass filter of 1Ω and 0.47 µF (minimum) is recommended. |
| VDDA | 7 | PWR | Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF ceramic capacitor from VDDA to power ground. |
| VSYS | 22 | PWR | Charger system voltage sensing. The system voltage regulation limit is programmed in REG0x05/04() and REG0X0D/0C(). |
| Thermal pad | – | – | Exposed pad beneath the IC. Analog ground and power ground star-connected near the IC's ground. Always solder thermal pad to the board, and have vias on the thermal pad plane connecting to power ground planes. It also serves as a thermal pad to dissipate the heat. |