ZHCSGD8A May 2017 – May 2018
PRODUCTION DATA.
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| I2C TIMING CHARACTERISTICS | |||||
| tr | SCLK/SDATA rise time | 1 | µs | ||
| tf | SCLK/SDATA fall time | 300 | ns | ||
| tW(H) | SCLK pulse width high | 4 | 50 | µs | |
| tW(L) | SCLK Pulse Width Low | 4.7 | µs | ||
| tSU(STA) | Setup time for START condition | 4.7 | µs | ||
| tH(STA) | START condition hold time after which first clock pulse is generated | 4 | µs | ||
| tSU(DAT) | Data setup time | 250 | ns | ||
| tH(DTA) | Data hold time | 300 | ns | ||
| tSU(STOP) | Setup time for STOP condition | 4 | µs | ||
| t(BUF) | Bus free time between START and STOP condition | 4.7 | µs | ||
| FS(CL) | Clock Frequency | 100 | 400 | KHz | |
| HOST COMMUNICATION FAILURE | |||||
| tBOOT | Deglitch for watchdog reset signal | 10 | ms | ||
| tWDI | Watchdog timeout period, ChargeOption() bit [6:5] = 01(1) | 35 | 44 | 53 | s |
| Watchdog timeout period, ChargeOption() bit bit [6:5] = 10(1) | 70 | 88 | 105 | s | |
| Watchdog timeout period, ChargeOption() bit bit [6:5] = 11(1) (default) | 140 | 175 | 210 | s | |