ZHCSGD8A May 2017 – May 2018
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power-Up from Battery Without DC Source
- 8.3.2 Power-Up From DC Source
- 8.3.3 USB On-The-Go (OTG)
- 8.3.4 Converter Operation
- 8.3.5 Current and Power Monitor
- 8.3.6 Input Source Dynamic Power Manage
- 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
- 8.3.8 Processor Hot Indication
- 8.3.9 Device Protection
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Map
- 8.6.1
Setting Charge and PROCHOT Options
- 8.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E20Eh]
- 8.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]
- 8.6.1.3 ChargeOption2 Register (I2C address = 33/32h) [reset = 2B7]
- 8.6.1.4 ChargeOption3 Register (I2C address = 35/34h) [reset = 0h]
- 8.6.1.5 ProchotOption0 Register (I2C address = 37/36h) [reset = 04A54h]
- 8.6.1.6 ProchotOption1 Register (I2C address = 39/38h) [reset = 8120h]
- 8.6.1.7 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
- 8.6.2 Charge and PROCHOT Status
- 8.6.3 ChargeCurrent Register (I2C address = 03/02h) [reset = 0h]
- 8.6.4 MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
- 8.6.5 MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
- 8.6.6 Input Current and Input Voltage Registers for Dynamic Power Management
- 8.6.7 OTGVoltage Register (I2C address = 07/06h) [reset = 0h]
- 8.6.8 OTGCurrent Register (I2C address = 09/08h) [reset = 0h]
- 8.6.9 ADCVBUS/PSYS Register (I2C address = 27/26h)
- 8.6.10 ADCIBAT Register (I2C address = 29/28h)
- 8.6.11 ADCIINCMPIN Register (I2C address = 2B/2Ah)
- 8.6.12 ADCVSYSVBAT Register (I2C address = 2D/2Ch)
- 8.6.13 ID Registers
- 8.6.1
Setting Charge and PROCHOT Options
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSN|32
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSN|32
訂購信息
8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and minimize battery discharge during CPU turbo mode. Peak power mode is enabled in REG0x33[5](EN_PKPWR_IDPM) or REG0x33[4](EN_PKPWR_VSYS). The DC current limit, or ILIM1, is the same as adapter DC current, set in REG0x0F/0E(). The overloading current, or ILIM2, is set in REG0x37[7:3], as a percentage of ILIM1.
When the charger detects input current surge and battery discharge due to load transient, it applies ILIM2 for TOVLD in REG0x33[7:6], first, and then ILIM1 for up to TMAX – TOVLD time. TMAX is programmed in REG0x33[1:0]. After TMAX, if the load is still high, another peak power cycle starts. Charging is disabled during TMAX,; once TMAX, expires, charging continues. If TOVLD is programmed higher than TMAX, then peak power mode is always on.
Figure 12. Two-Level Adapter Current Limit Timing Diagram