ZHCSGD8A May 2017 – May 2018
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power-Up from Battery Without DC Source
- 8.3.2 Power-Up From DC Source
- 8.3.3 USB On-The-Go (OTG)
- 8.3.4 Converter Operation
- 8.3.5 Current and Power Monitor
- 8.3.6 Input Source Dynamic Power Manage
- 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
- 8.3.8 Processor Hot Indication
- 8.3.9 Device Protection
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Map
- 8.6.1
Setting Charge and PROCHOT Options
- 8.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E20Eh]
- 8.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]
- 8.6.1.3 ChargeOption2 Register (I2C address = 33/32h) [reset = 2B7]
- 8.6.1.4 ChargeOption3 Register (I2C address = 35/34h) [reset = 0h]
- 8.6.1.5 ProchotOption0 Register (I2C address = 37/36h) [reset = 04A54h]
- 8.6.1.6 ProchotOption1 Register (I2C address = 39/38h) [reset = 8120h]
- 8.6.1.7 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
- 8.6.2 Charge and PROCHOT Status
- 8.6.3 ChargeCurrent Register (I2C address = 03/02h) [reset = 0h]
- 8.6.4 MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
- 8.6.5 MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
- 8.6.6 Input Current and Input Voltage Registers for Dynamic Power Management
- 8.6.7 OTGVoltage Register (I2C address = 07/06h) [reset = 0h]
- 8.6.8 OTGCurrent Register (I2C address = 09/08h) [reset = 0h]
- 8.6.9 ADCVBUS/PSYS Register (I2C address = 27/26h)
- 8.6.10 ADCIBAT Register (I2C address = 29/28h)
- 8.6.11 ADCIINCMPIN Register (I2C address = 2B/2Ah)
- 8.6.12 ADCVSYSVBAT Register (I2C address = 2D/2Ch)
- 8.6.13 ID Registers
- 8.6.1
Setting Charge and PROCHOT Options
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
9.2.2.3 Input Capacitor
Bulk input capacitors should be locate in front of input current sensing resistor. Do not recommend to put bulk input capacitors between input sensing resistor and switching MOSFET. Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 5:
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred for 19 V - 20 V input voltage. Minimum 10-µF effective capacitance (7 pcs of 10-µF 0805 size capacitor) is suggested for 45 W-65 W adapter.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's datasheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.