ZHCSJZ6F June 2019 – February 2025 BQ25618 , BQ25619
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 說明（續(xù)）
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Power-On-Reset (POR)
- 7.3.2 Device Power Up From Battery Without Input Source
- 7.3.3 Power Up From Input Source
- 7.3.4 Boost Mode Operation From Battery
- 7.3.5 Power Path Management
- 7.3.6 Battery Charging Management
- 7.3.7 Ship Mode and QON Pin
- 7.3.8 Status Outputs (STAT, INT , PMID_GOOD)
- 7.3.9 Protections
- 7.3.10 Serial Interface
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購信息
7.3.10.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Figure 7-9 Data Transfer on the I2C Bus