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ZHCSBN3F August 2013 – March 2019

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGR|20
- MPQF239A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGR|20
- QFND242E

訂購(gòu)信息

8.2.1.3 Application Performance Plots

bq25505 app1_startup_1VIN_8p5ma_100kohm_slusbj3.png

Sourcemeter with V_SOURCE = 1.0 V and compliance of 8.5 mA subsequently applied to VIN_DC

VBAT_SEC = 0.1 F capacitor charged to 2.0 V

Resistance on VSTOR = 100 kΩ

Figure 17. Startup by Battery Attach With Almost Depleted Storage Element

bq25505 app1_mppt_ov_4p2v_3vstor_2p0vin_42p6ma_slusbj3.png

VIN_DC = sourcemeter with V_SOURCE = 2.0 V and compliance of 43 mA

VBAT_SEC = sourcemeter with V_SOURCE = 3.0 V and compliance of 1 A

Figure 19. MPPT Operation

bq25505 bq25570_bq25505-vbat-ok1_lusbh2.gif

VIN_DC = 1.5 V with 75 Ω series resistance

No storage element on VBAT_SEC or VBAT_PRI

VSTOR artifically ramped from 0 V to 4.2 V to 0 V using a power amp driven by a function generator

Figure 21. VBAT_OK Operation

VIN_DC = 1.5 V with 75 Ω series resistance

VBAT = 4.2 V charged 0.5 F capacitor

R(VSTOR) = open to 84 Ω to open

Figure 23. 50 mA Load Transient on VSTOR - Zoom Out

bq25505 bq25505-ds27-multi-pri-hi-3P6V.png

VIN_DC = 1.5 V with 75 Ω series resistance; VBAT _PRI = 3.6 V power supply

0.5 F super capacitor on VBAT_SEC; 1kΩ load on output of MUX FETs (VOR)

VSTOR artifically ramped from 0 V to 4.2 V using a function generator

Figure 25. MUX Signals When VBAT_SEC > VBAT_OK Threshold

bq25505 IIN_1mA_VOC_1p2V_CSTOR_100uF_VBAT_supcap_0p12F_1.png

VIN_DC = source meter with 1.2 V compliance and ISC = 1 mA

120 mF super capacitor on VBAT_SEC

Figure 27. Charging a Super Capacitor on VBAT

bq25505 app2_operation_ov_5p0v_3vstor_2p0vin_42p6ma_slusbj3.png

VIN_DC = sourcemeter with V_SOURCE = 2.0 V and compliance of 43 mA

VBAT_SEC = sourcemeter with V_SOURCE = 3.0 V and compliance of 1 A

IL = inductor current

Figure 18. Boost Charger Operational Waveforms

VIN_DC = sourcemeter with V_SOURCE = 2.0 V and compliance of 43 mA

VBAT_SEC = sourcemeter with V_SOURCE = 3.6 V and compliance of 1 A

Figure 20. VRDIV Waveform

VIN_DC = 1.5 V with 75 Ω series resistance

VBAT = 4.2 V charged 0.5 F capacitor

R(VSTOR) = open to 84 Ω to open

Figure 22. 50 mA Load Transient on VSTOR

VIN_DC = 1.5 V with 75 Ω series resistance; VBAT _PRI = 3.6 V power supply

0.5 F super capacitor on VBAT_SEC; 1kΩ load on output of MUX FETs (VOR)

VSTOR artifically ramped from 0 V to 4.2 V to 0 V using a function generator

Figure 24. Multiplexer Output (VOR) as VBAT_SEC Crosses VBAT_OK Threshold

bq25505 bq25505-ds28-multi-pri-lo-3P6V.png

VIN_DC = 1.5 V with 75 Ω series resistance; VBAT _PRI = 3.6 V power supply

0.5 F super capacitor on VBAT_SEC; 1kΩ load on output of MUX FETs (VOR)

VSTOR artifically ramped from 4.2 V to 0 V using a function generator

Figure 26. MUX Signals When VBAT_SEC < VBAT_OK Threshold