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ZHCSN86A May 2021 – September 2021 AMC1411

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DWL|8
- MPSS116

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsn86a_oa

6.9 Electrical Characteristics

minimum and maximum specifications apply from T_A = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, V_IN = –0.1 V to 2 V, and SHTDN = GND1 = 0 V (unless otherwise noted); typical specifications are at T_A = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
V_OS	Input offset voltage	T_A = 25°C⁽¹⁾ ⁽²⁾	–1.5	±0.1	1.5	mV
TCV_OS	Input offset thermal drift⁽¹⁾ ⁽²⁾ ⁽⁴⁾		–10	±3	10	μV/°C
R_IN	Input resistance	T_A = 25℃		1		G?
I_IB	Input bias current	IN = GND1, T_A = 25℃	–15	3.5	15	nA
C_IN	Input capacitance	f_IN = 275 kHz		7		pF
ANALOG OUTPUT
	Nominal gain			1		V/V
E_G	Gain error⁽¹⁾	T_A = 25℃	–0.2	±0.05	0.2	%
TCE_G	Gain error drift⁽¹⁾ ⁽⁵⁾		–30	±5	30	ppm/°C
	Nonlineartity⁽¹⁾		–0.04%	±0.01%	0.04%
THD	Total harmonic distortion⁽³⁾	V_IN = 2 V_PP, V_IN > 0 V, f_IN = 10 kHz, BW = 10 kHz		–87		dB
SNR	Signal-to-noise ratio	V_IN = 2 V_PP, f_IN = 1 kHz, BW = 10 kHz	79	82.6		dB
SNR	Signal-to-noise ratio	V_IN = 2 V_PP, f_IN = 10 kHz, BW = 100 kHz		70.9		dB
	Output noise	V_IN = GND1, BW = 100 kHz		220		μVrms
PSRR	Power-supply rejection ratio⁽²⁾	vs VDD1, at DC		–80		dB
		vs VDD2, at DC		–85
		vs VDD1, 10 kHz / 100-mV ripple		–65
		vs VDD2, 10 kHz / 100-mV ripple		–70
V_CMout	Output common-mode voltage		1.39	1.44	1.49	V
V_CLIPout	Clipping differential output voltage	V_OUT = (V_OUTP – V_OUTN); V_IN > V_Clipping		2.49		V
V_FAILSAFE	Failsafe differential output voltage	SHTDN = high, or VDD1 undervoltage, or VDD1 missing		–2.6	–2.5	V
BW	Output bandwidth		220	275		kHz
R_OUT	Output resistance	On OUTP or OUTN		<0.2		Ω
	Output short-circuit current	On OUTP or OUTN, sourcing or sinking, IN = GND1, outputs shorted to either GND or VDD2		14		mA
CMTI	Common-mode transient immunity		100	150		kV/μs
DIGITAL INPUT
I_IN	Input current	SHTDN pin, GND1 ≤ SHTDN ≤ VDD1	–70		1	μA
C_IN	Input capacitance	SHTDN pin		5		pF
V_IH	High-level input voltage		0.7 × VDD1			V
V_IL	Low-level input voltage				0.3 × VDD1	V
POWER SUPPLY
VDD1_UV	VDD1 undervoltage detection threshold	VDD1 rising	2.5	2.7	2.9	V
VDD1_UV	VDD1 undervoltage detection threshold	VDD1 falling	2.4	2.6	2.8	V
VDD2_UV	VDD2 undervoltage detection threshold	VDD2 rising	2.2	2.45	2.65	V
VDD2_UV	VDD2 undervoltage detection threshold	VDD2 falling	1.85	2.0	2.2	V
I_DD1	High-side supply current	3.0 V < VDD1 < 3.6 V		6.0	8.4	mA
		4.5 V < VDD1 < 5.5 V, SHTDN = low		7.1	9.7	mA
		SHTDN = VDD1		1.3		μA
I_DD2	Low-side supply current	3.0 V < VDD2 < 3.6 V		5.3	7.2	mA
I_DD2	Low-side supply current	4.5 V < VDD2 < 5.5 V		5.9	8.1	mA

(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.

(2) This parameter is input referred.

(3) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.

(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCV_OS = (Value_MAX - Value_MIN) / TempRange

(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCE_G (ppm) = (Value_MAX - Value_MIN) / (Value_(T=25℃) x TempRange) x 10⁶