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ZHCS161D April 2011 – July 2015 AMC1200

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DUB|8
- MPDS247D
DWV|8
- MPDS382B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DUB|8
- QFND302E

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

Over the operating ambient temperature range, unless otherwise noted.⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, VDD1 to GND1 or VDD2 to GND2	–0.5	6	V
Analog input voltage at VINP, VINN	GND1 – 0.5	VDD1 + 0.5	V
Input current to any pin except supply pins	–10	10	mA
Maximum junction temperature, T_J Max		150	°C
Storage Temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM) JEDEC standard 22, test method A114-C.01⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
T_A	Operating ambient temperature range	–40		105	°C
VDD1	High-side power supply	4.5	5	5.5	V
VDD2	Low-side power supply	2.7	5	5.5	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		AMC1200, AMC1200B		UNIT
		DUB (SOP)	DWV (SOIC)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	75.1	102.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	61.6	49.8	°C/W
R_θJB	Junction-to-board thermal resistance	39.8	56.6	°C/W
ψ_JT	Junction-to-top characterization parameter	27.2	16	°C/W
ψ_JB	Junction-to-board characterization parameter	39.4	55.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All minimum/maximum specifications at T_A = –40°C to 105°C and within the specified voltage range, unless otherwise noted. Typical values are at T_A = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT
	Maximum input voltage before clipping	VINP – VINN		±320		mV
	Differential input voltage	VINP – VINN	–250		250	mV
V_CM	Common mode operating range		–0.16		VDD1	V
V_OS	Input offset voltage		–1.5	±0.2	1.5	mV
TCV_OS	Input offset thermal drift		–10	±1.5	10	µV/K
CMRR	Common mode rejection ratio	V_IN from 0 V to 5 V at 0 Hz		108		dB
CMRR	Common mode rejection ratio	V_IN from 0 V to 5 V at 50 kHz		95		dB
C_IN	Input capacitance to GND1	VINP or VINN		3		pF
C_IND	Differential input capacitance			3.6		pF
R_IN	Differential input resistance			28		kΩ
	Small-signal bandwidth		60	100		kHz
OUTPUT
	Nominal gain			8
G_ERR	Gain error	Initial, at T_A = 25°C	–0.5%	±0.05%	0.5%
G_ERR	Gain error		–1%	±0.05%	1%
TCG_ERR	Gain error thermal drift			±56		ppm/K
	Nonlinearity	4.5 V ≤ VDD2 ≤ 5.5 V	–0.075%	±0.015%	0.075%
	Nonlinearity	2.7 V ≤ VDD2 ≤ 3.6 V	–0.1%	±0.023%	0.1%
	Nonlinearity thermal drift			2.4		ppm/K
	Output noise	VINP = VINN = 0 V		3.1		mV_RMS
PSRR	Power-supply rejection ratio	vs VDD1, 10-kHz ripple		80		dB
PSRR	Power-supply rejection ratio	vs VDD2, 10-kHz ripple		61		dB
	Rise/fall time	0.5-V step, 10% to 90%		3.66	6.6	µs
	V_IN to V_OUT signal delay	0.5-V step, 50% to 10%, unfiltered output		1.6	3.3	µs
		0.5-V step, 50% to 50%, unfiltered output		3.15	5.6	µs
		0.5-V step, 50% to 90%, unfiltered output		5.26	9.9	µs
CMTI	Common mode transient immunity	V_CM = 1 kV	10	15		kV/µs
	Output common mode voltage	2.7 V ≤ VDD2 ≤ 3.6 V	1.15	1.29	1.45	V
	Output common mode voltage	4.5 V ≤ VDD2 ≤ 5.5 V	2.4	2.55	2.7	V
	Short circuit current			20		mA
R_OUT	Output resistance			2.5		Ω
POWER SUPPLY
VDD1	High-side supply voltage		4.5	5	5.5	V
VDD2	Low-side supply voltage		2.7	5	5.5	V
I_DD1	High-side supply current			5.4	8	mA
I_DD2	Low-side supply current	2.7 V < VDD2 < 3.6 V		3.8	6	mA
I_DD2	Low-side supply current	4.5 V < VDD2 < 5.5 V		4.4	7	mA
P_DD1	High-side power dissipation			27	44	mW
P_DD2	Low-side power dissipation	2.7 V < VDD2 < 3.6 V		11.4	21.6	mW
P_DD2	Low-side power dissipation	4.5 V < VDD2 < 5.5 V		22	38.5	mW