ZHCSR25 August 2022 ADC3564
PRODUCTION DATA
The digital output interface utilizes a flexible output bit mapper as shown in Figure 8-33. The bit mapper takes the 14-bit output directly from the ADC or from digital filter block and reformats it to a resolution of 14, 16, 18 or 20-bit. The output serialization factor gets adjusted accordingly for 2-, 1- and 1/2-wire interface modes. The maximum SLVDS interface output data rate can not be exceeded independent of output resolution or serialization factor.
When using a higher resolution like 16-bit output for example in non-decimation mode, the 2 LSBs are set to 0.
Table 8-5 provides an overview for the resulting serialization factor depending on output resolution and output modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output resolution to 16-bit, 2-wire mode for example would result in DCLKIN = FS * 4 instead of * 3.5.
The output bit mapper can be used for bypass and decimation filter.
| OUTPUT RESOLUTION | Interface | SERIALIZATION | FCLK | DCLKIN | DCLK | D0/D1 |
|---|---|---|---|---|---|---|
| 14-bit (default) | 2-Wire | 7x | FS/2 | FS* 3.5 | FS* 3.5 | FS* 7 |
| 1-Wire | 14x | FS | FS* 7 | FS* 7 | FS* 14 | |
| 1/2-Wire | 28x | FS | FS* 14 | FS* 14 | FS* 28 | |
| 16-bit | 2-Wire | 8x | FS/2 | FS* 4 | FS* 4 | FS* 8 |
| 1-Wire | 16x | FS | FS* 8 | FS* 8 | FS* 16 | |
| 1/2-Wire | 32x | FS | FS* 16 | FS* 16 | FS* 32 | |
| 18-bit | 2-Wire | 9x | FS/2 | FS* 4.5 | FS* 4.5 | FS* 9 |
| 1-Wire | 18x | FS | FS* 9 | FS* 9 | FS* 18 | |
| 1/2-Wire | 36x | FS | FS* 18 | FS* 18 | FS* 36 | |
| 20-bit | 2-Wire | 10x | FS/2 | FS* 5 | FS* 5 | FS* 10 |
| 1-Wire | 20x | FS | FS* 10 | FS* 10 | FS* 20 | |
| 1/2-Wire | 40x | FS | FS* 20 | FS* 20 | FS* 40 |
The programming sequence to change the output interface and/or resolution from default settings is shown in Section 8.3.5.3.