The ADC3564 requires two different power-supplies. The AVDD rail provides power for the internal analog circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like decimation filter or output interface mapper. Power sequencing is not required.

The AVDD power supply must be low noise to achieve data sheet performance. In applications operating near DC, the 1/f noise contribution of the power supply must also be considered. The ADC is designed for good PSRR which aides with the power supply filter design.

There are two recommended power-supply architectures:

1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low noise LDO to provide switching noise reduction and improved voltage accuracy.
2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach provides the best efficiency, but care must be taken to make sure the switching noise is minimized to prevent degraded ADC performance.

TI WEBENCH? Power Designer can be used to select and design the individual power-supply elements needed: see the WEBENCH? Power Designer

Recommended switching regulators for the first stage include the TPS62821, and similar devices.

Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar devices.

For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH? and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure 9-8 and Figure 9-9 illustrate the two approaches.

AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling into the analog signal chain.

Figure 9-8 Example: LDO Linear Regulator Approach

Figure 9-9 Example Switcher-Only Approach