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ZHCSNC3B February 2021 – October 2022 ADC3561 , ADC3562 , ADC3563

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- MPQF185C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- QFND255H

訂購信息

8.3.5.2 Output Bit Mapper

The output bit mapper allows change to the output bit order for any selected interface mode.

Figure 8-42 Output Bit Mapper

There is a two step process to change the output bit mapping and assemble the output data bus:

Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier bit as shown in Table 8-7. The MSB starts with bit D19 – depending on output resolution chosen the LSB would be D6 (14-bit) to D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
The bit mapper is then used to assemble the output sample. The following sections detail how to remap the serial output format.

Table 8-7 Unique identifier of each data bit

Bit	Channel A		Channel B
	Previous sample (2w only)	Current sample	Previous sample (2w only)	Current sample
D19 (MSB)	0x2D	0x6D	0x29	0x69
D18	0x2C	0x6C	0x28	0x68
D17	0x27	0x67	0x23	0x63
D16	0x26	0x66	0x22	0x62
D15	0x25	0x65	0x21	0x61
D14	0x24	0x64	0x20	0x60
D13	0x1F	0x5F	0x1B	0x5B
D12	0x1E	0x5E	0x1A	0x5A
D11	0x1D	0x5D	0x19	0x59
D10	0x1C	0x5C	0x18	0x58
D9	0x17	0x57	0x13	0x53
D8	0x16	0x56	0x12	0x52
D7	0x15	0x55	0x11	0x51
D6	0x14	0x54	0x10	0x50
D5	0x0F	0x4F	0x0B	0x4B
D4	0x0E	0x4E	0x0A	0x4A
D3	0x0D	0x4D	0x09	0x49
D2	0x0C	0x4C	0x08	0x48
D1	0x07	0x47	0x03	0x43
D0 (LSB)	0x06	0x46	0x02	0x42

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address 0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode both the current and the previous sample have to be used in the address space as shown in Figure 8-43. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (gray back ground), which can be ignored if not used.

Figure 8-43 2-wire output bit mapper

In the following example (Figure 8-44), the 16-bit 2-wire serial output is reordered to where lane DA1/DB1 carries the 8 MSB and lane DA0/DB0 carries 8 LSBs.

Figure 8-44 Example: 2-wire output bit mapping

1-wire mode: Only the ‘current’ sample needs to programmed in the address space. If desired, it can be duplicated on DA1/DB1 as well (using addresses shown below) in order to have a redundant output. Lane DA1/DB1 needs to be powered up in that case.

Figure 8-45 1-wire output bit mapping

?-wire mode: The output is only lane DA0 and the sample order is programmed into the 40 addresses of chA (from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown below. If desired, it can be duplicated on DB0 as well (using addresses shown Figure 8-46) in order to have a redundant output. Lane DB0 needs to be powered up in that case.

Figure 8-46 1/2-wire output bit mapping