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ZHCSLJ1C July 2020 – December 2022 ADC3541 , ADC3542 , ADC3543

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RSB|40
- MPQF185C

散熱焊盤機械數據 (封裝 | 引腳)

RSB|40
- QFND255H

訂購信息

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
No missing codes			14			bits
PSRR		F_IN = 1 MHz		38		dB
ADC3541 - 10 MSPS: DC ACCURACY
DNL	Differential nonlinearity	F_IN = 1.1 MHz		± 0.2	± 0.85	LSB
INL	Integral nonlinearity	F_IN = 1.1 MHz		± 0.6	± 2.1	LSB
V_{OS_ERR}	Offset error			12	130	LSB
V_{OS_DRIFT}	Offset drift over temperature			0.01		LSB/oC
GAIN_ERR	Gain error	External 1.6 V reference		0.5		%FSR
GAIN_DRIFT	Gain drift over temperature	External 1.6 V reference		25		ppm/oC
GAIN_ERR	Gain error	Internal reference		-2.3		%FSR
GAIN_DRIFT	Gain drift over temperature	Internal reference		151		ppm/oC
Transition Noise				0.45		LSB_RMS
ADC3542 - 25 MSPS: DC ACCURACY
DNL	Differential nonlinearity	F_IN = 1.1 MHz		± 0.2	± 0.85	LSB
INL	Integral nonlinearity	F_IN = 1.1 MHz		± 0.6	± 2.1	LSB
V_{OS_ERR}	Offset error			12	130	LSB
V_{OS_DRIFT}	Offset drift over temperature			-0.01		LSB/oC
GAIN_ERR	Gain error	External 1.6 V reference		-0.2		%FSR
GAIN_DRIFT	Gain drift over temperature	External 1.6 V reference		31		ppm/oC
GAIN_ERR	Gain error	Internal reference		-2.8		%FSR
GAIN_DRIFT	Gain drift over temperature	Internal reference		151		ppm/oC
Transition Noise				0.45		LSB_RMS
ADC3543 - 65 MSPS: DC ACCURACY
DNL	Differential nonlinearity	F_IN = 5 MHz		± 0.1	± 0.75	LSB
INL	Integral nonlinearity	F_IN = 5 MHz		± 0.6	± 4.3	LSB
V_{OS_ERR}	Offset error			5.9	55	LSB
V_{OS_DRIFT}	Offset drift over temperature			0.02		LSB/oC
GAIN_ERR	Gain error	External 1.6 V reference		0.7		%FSR
GAIN_DRIFT	Gain drift over temperature	External 1.6 V reference		25		ppm/oC
GAIN_ERR	Gain error	Internal reference		0.8		%FSR
GAIN_DRIFT	Gain drift over temperature	Internal reference		96		ppm/oC
Transition Noise				0.45		LSB_RMS
ADC ANALOG INPUT (AINP/M)
FS	Input full scale	Default, differential		2.25		Vpp
V_CM	Input common mode voltage		0.9	0.95	1.0	V
R_IN	Differential input resistance	F_IN = 100 kHz		8		kΩ
C_IN	Differential input capacitance	F_IN = 100 kHz		7		pF
V_OCM	Output common mode voltage			0.95		V
BW	Analog input bandwidth (-3dB)			900		MHz
Internal Voltage Reference
V_REF	Internal reference voltage			1.6		V
V_REFOutput Impedance				8		Ω
Reference Input Buffer (REFBUF)
External reference voltage				1.2		V
External voltage reference (VREF)
V_REF	External voltage reference			1.6		V
Input Current				0.3		mA
Input impedance				5.3		kΩ
Clock Input (CLKP/M)
Input clock frequency			0.5		65	MHz
V_ID	Differential input voltage			1	3.6	Vpp
V_CM	Input common mode voltage			0.9		V
R_IN	Single ended input resistance to common mode			5		kΩ
C_IN	Single ended input capacitance			1.5		pF
Clock duty cycle			40	50	60	%
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
V_IH	High level input voltage		1.5			V
V_IL	Low level input voltage				0.4	V
I_IH	High level input current			90	150	uA
I_IL	Low level input current		-150	90		uA
C_I	Input capacitance			1.5		pF
Digital Output (SDOUT)
V_OH	High level output voltage	I_LOAD = -400 uA	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
CMOS Interface (D0:D17)
Output data rate		per CMOS output pin			250	MHz
V_OH	High level output voltage	I_LOAD = -400 uA	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
V_IH	High level input voltage	Input clock (Serial CMOS)	IOVDD – 0.1	IOVDD		V
V_IL	Low level input voltage	Input clock (Serial CMOS)			0.1	V