5 Pin Configuration and Functions

Figure 5-1 RSB Package, 40-Pin WQFN
(Top View)

Table 5-1 Pin Descriptions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
INPUT/REFERENCE
AINM	14	I	Negative analog input
AINP	13	I	Positive analog input
REFBUF	4	I	1.2-V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND	3	I	Reference ground input, 0 V
VCM	9	O	Common-mode voltage output for the analog inputs, 0.95 V
VREF	2	I	External voltage reference input, 1.6 V.
CLOCK
CLKM	7	I	Negative differential sampling clock input for the ADC
CLKP	6	I	Positive differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC	1	I	Power down, synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET	10	I	Hardware reset; active high. This pin has an internal 21 kΩ pull-down resistor.
SCLK	40	I	Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO	39	I	Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
SEN	17	I	Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
DIGITAL INTERFACE
DCLK	26	O	CMOS output for data bit clock.
D0	38	O	SDR CMOS output used with 18 bit output (configured via output bit formatter). This becomes the LSB. When not used it can be left unconnected. See Section 8.3.5.4 and Section 8.3.5.5 on how to change the output resolution and output bit mapping.
D1	37	O	SDR CMOS output used with 16 bit output (configured via output bit formatter). This becomes the LSB. When not used it can be left unconnected.
D2	36	O	SDR CMOS output for data bit D0 (14 bit LSB).
D3/ DCLKIN	35	I/O	SDR CMOS output for data bit D1. Used as DCLKIN for serial CMOS output modes.
D4	34	O	SDR CMOS output for data bit D2.
D5	33	O	SDR CMOS output for data bit D3.
D6	32	O	SDR CMOS output for data bit D4.
D7	30	O	SDR CMOS output for data bit D5.
D8	29	O	SDR CMOS output for data bit D6.
D9	28	O	SDR CMOS output for data bit D7.
D10	27	O	SDR CMOS output for data bit D8.
D11/ Serial Lane 0	24	O	SDR CMOS output for data bit D9. DDR CMOS output for data bits D6/D13 (MSB). Lane 0 in serial CMOS output mode.
D12/ Serial Lane 1	23	O	SDR CMOS output for data bit D10. DDR CMOS output for data bits D5/D12. Lane 1 in serial CMOS output mode.
D13	22	O	SDR CMOS output for data bit D11. DDR CMOS output for data bits D4/D11.
D14	21	O	SDR CMOS output for data bit D12. DDR CMOS output for data bits D3/D10.
D15	20	O	CMOS output for data bit D13 (MSB). DDR CMOS output for data bits D2/D9.
D16/ FCLK	19	O	SDR CMOS output used with 16 bit output (configured via output bit formatter). This becomes the MSB. When not used it can be left unconnected. DDR CMOS output for data bits D1/D8. Frame clock output in serial CMOS output mode.
D17	18	O	SDR CMOS output used with 18 bit output (configured via output bit formatter). This becomes the MSB. When not used it can be left unconnected. DDR CMOS output for data bits D0/D7 (LSB).
POWER SUPPLY
AVDD	5,8,11,16	I	Analog 1.8-V power supply
GND	12,15	I	Ground, 0 V
IOGND	25	I	Ground, 0 V for digital interface
IOVDD	31	I	1.8-V power supply for digital interface
PowerPAD?	--	--	Connect to ground.