ZHCSPO3 March 2023 ADC34RF52
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - AC Specifications (Dither ENABLED)
- 6.9 Timing Requirements
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6 JESD204B Interface
- 7.3.7 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application Information Disclaimer
- 8.1 Application Information
- 8.2 Typical Application
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 Step 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
訂購信息
7.4.2 Digital Averaging
The ADC34RF52 provides a total of eight internal single core 1.5 Gsps ADCs. The normal operating mode uses only four ADC cores (one ADC per channel). The four additional ADC cores can be enabled to trade off additional noise density improvement against a small power increase. Figure 7-42 shows the internal block diagram in digital averaging mode where one external input is connected to 2 ADC cores internally.
Figure 7-42 Internal Digital AveragingTable 7-44 provides a trade-off comparison of digital averaging mode vs the non-averaged mode (default).
| # of ADCs averaged | Input Bandwidth (-3 dB) | Effective input termination | Noise density | Power/ch (W) |
|---|---|---|---|---|
| Default | 1.6 GHz | 100 Ω | -153 dBFS/Hz | 0.7 |
| 2 | 1.5 GHz | 100 Ω | -156 dBFS/Hz | 1.0 |
Digital averaging improves decorrelated noise contributions by 3 dB per 2x AVG (ideal) while correlated noise does not improve with averaging. Some of the dominant noise sources are correlated (that is, clock jitter (external or first clock input buffer) or power supply noise) while others (that is, ADC thermal noise, clock distribution buffers) are decorrelated.
SNR: When operating close to ADC full scale, some of the SNR limitation is due to jitter and hence the SNR improvement won’t reach 3 dB (2x AVG). As the input full scale is reduced, the clock jitter contribution to SNR becomes less and the SNR improvement is approaching the ideal 3 dB per 2x AVG. The same phenomenon can be observed when using digital decimation. As the decimation factor increases, the close-in (correlated noise) becomes the more dominating noise unless the input signal amplitude is reduced.
SFDR: The amplitude of low order harmonics (HD2-HD5) and IMD3 typically is similar across ADCs, and thus, the improvement with averaging is small.