The ADC34RF52 is a single core (non-interleaved) 14-bit, 1.5 GSPS, quad channel analog to digital converter (ADC).The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Additional internal ADCs can be used for on-chip averaging to further improve the noise density to as low as -156 dBFS/Hz.

The analog signal input is non-buffered to save power consumption with a nominal differential input impedance of 100 Ω. The full power input bandwidth is 1.6 GHz (-3dB) and the device supports direct RF sampling with input frequencies through the L-band. The device is designed for low residual phase noise to support high performance radar applications. The sampling clock input has a dedicated power supply input which requires a clean power supply.

Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping is achieved in less than 1 μs. The digital down converters support a wide range of instantaneous bandwidth (IBW) coverage. A single wide band mode with 4x complex decimation up to two narrow bandwidth channels with as high as 128x complex decimation.

The ADC34RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13.0 GBPS. The device is pin-pin compatible with the ADC34RF54 (2.6 GSPS) and ADC34RF55 (3 GSPS).

The power efficient ADC architecture consumes 0.73 W/ch at 1.5 GSPS at maximum sampling rate and provides power scaling with lower sampling rates (0.55 W/ch at 0.6 GSPS).