4 修訂歷史記錄

Changes from A Revision (October 2015) to B Revision

• Added 在 說明部分添加了有關可提供單線制串行 LVDS 接口的說明Go
• Changed 10MHz 時的頻譜圖，顯示曲線內的情況Go
• Changed description of AVDD, DVDD, and GND pins and added active high to description of PDN pin in Pin Functions tableGo
• Deleted maximum from parameter description in Recommended Operating Conditions table Go
• Changed Digital Outputs, R_LOAD parameter description in Recommended Operating Conditions table Go
• Changed conditions of all Electrical Characteristics and AC Performance tablesGo
• Added minimum and maximum specifications to Analog Input, V_OC(VCM) parameter in Electrical Characteristics: General tableGo
• Changed description of Analog Input, Analog input bandwidth parameter in Electrical Characteristics: General tableGo
• Deleted footnote 1 from Electrical Characteristics: General tableGo
• Added DC Accuracy, E_G parameter with its test conditions and footnote 3 to Electrical Characteristics: General tableGo
• Deleted E_G(REF) and E_G(CHAN) from DC Accuracy in Electrical Characteristics: General table Go
• Changed DC Accuracy, α_(EGCHAN) to α_EG and updated its parameter in Electrical Characteristics: General tableGo
• Changed Channel-to-Channel Isolation, Crosstalk parameter in Electrical Characteristics: General table: changed test conditions, added footnote 2Go
• Changed test conditions for IMD3 parameter in AC Performance: ADC3441 tableGo
• Added INL and DNL rows to all AC Performance tablesGo
• Changed Digital Inputs (SYSREFP, SYSREFM) subsection in Digital Characteristics table, added footnote 2Go
• Changed specifications of Digital Outputs (LVDS Interface), V_OCM parameter in Digital Characteristics tableGo
• Changed rising to falling in description of SYSREF reference time parameter in Timing Requirements: General table Go
• Changed Typical Characteristics sections: added dither on to all section condition statements, changed Non 23 to excluding HD2, HD3Go
• Added INL and DNL plots in Typical Characteristics: ADC3441 sectionGo
• Changed conditions of Figure 34, Figure 35Go
• Added INL and DNL plots in Typical Characteristics: ADC3442 section Go
• Changed conditions of Figure 67, Figure 68Go
• Added INL and DNL plots in Typical Characteristics: ADC3443 section Go
• Changed conditions of Figure 100, Figure 101Go
• Added INL and DNL plots in Typical Characteristics: ADC3444 section. Go
• Changed conditions of Figure 134 Go
• Added Figure 141 to Timing Diagrams sectionGo
• Added Using the SYSREF Input sectionGo
• Changed the description about synchronization of the phase of the divided clock in each device to the common sampling clock in Using the SYSREF Input section. Go
• Added ADC3441 Power-Up Requirements section, deleted the Register Initialization sectionGo
• Added last sentence to Detailed Design Procedure section of first typical applicationGo
• Added Chopper On to caption of Figure 198 Go
• Added Chopper Off to caption of Figure 200 Go
• Changed the caption of Figure 202 from FFT for 450-MHz Input Signal (Dither On) to FFT for 450-MHz Input Signal (Chopper Off, Dither On)Go

Changes from * Revision (July 2014) to A Revision

• 已發布量產Go