9.3.1 Analog Inputs

The ADC344x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω termination between INP and INM).

9.3.2 Clock Input

The device clock inputs may be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors. The ADC344x self-bias clock inputs may be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 145, Figure 146, and Figure 147. See Figure 148 for details regarding the internal clock buffer.

NOTE: R_T = termination resistor, if necessary.

Figure 145. Differential Sine-Wave Clock Driving Circuit

Figure 146. LVDS Clock Driving Circuit

Figure 147. LVPECL Clock Driving Circuit

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 148. Internal Clock Buffer

A single-ended CMOS clock may be ac-coupled to the CLKP input, with CLKM connected to ground with a
0.1-μF capacitor, as shown in Figure 149. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with low jitter. Band-pass filtering of the clock source may help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 149. Single-Ended Clock Driving Circuit

9.3.2.1 Using the SYSREF Input

The ADC344x has a SYSREF input pin that can be used when the clock-divider feature is used. A logic low-to-high transition on the SYSREF pin aligns the falling edge of the divided clock with the next falling edge of the input clock, essentially resetting the phase of the divided clock, as shown in Figure 150. When multiple ADC344x devices are onboard and the clock divider option is used, the phase of the divided clock among the devices may not be the same. The phase of the divided clock in each device can be synchronized to the common sampling clock by using the SYSREF pins. SYSREF can applied as mono-shot or periodic waveform. When applied as periodic waveform, its period must be integer multiple of period of the divided clock. When not used, the SYSREFP and SYSREFM pins can be connected to AVDD and GND, respectively. Alternatively, the SYSREF buffer inside the device can be powered down using the PDN SYSREF register bit.

Figure 150. Using SYSREF for Synchronization

9.3.2.2 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies.

Equation 1.

The SNR limitation resulting from sample clock jitter may be calculated with Equation 2.

Equation 2.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs for the device) which is set by the noise of the clock input buffer and the external clock. T_Jitter may be calculated with Equation 3.

Equation 3.

External clock jitter may be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The devices have a typical thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 151.

Figure 151. SNR vs Frequency for Different Clock Jitter

9.3.3 Digital Output Interface

The devices offer two different output format options, thus making interfacing to a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) easy. Each option may be easily programmed using the serial interface, as shown in Table 3. The output interface options are:

• One-wire, 1x frame clock, 14x serialization with the DDR bit clock
• Two-wire, 1x frame clock, 7x serialization with the DDR bit clock.

9.3.3.2 Two-Wire Interface: 7x Serialization

The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as shown in Figure 152.

Figure 152. Output Timing Diagram

9.4.1 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider may be bypassed for operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the divide-by-4 option provides a maximum input clock frequency of 500 MHz.

9.4.2 Chopper Functionality

The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC noise spectrum by shifting the 1/f noise from dc to f_S / 2. Figure 153 shows the noise spectrum with the chopper off and Figure 154 shows the noise spectrum with the chopper on. This function is especially useful in applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper may be enabled through SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function creates a spur at f_S / 2 that must be filtered out digitally.

fS = 125 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz, SFDR = 94 dBc

Figure 153. Chopper Off

fS = 125 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz, SFDR = 94 dBc

Figure 154. Chopper On

9.4.3 Power-Down Control

The ADC344x power-down functions may be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin may also be configured through SPI to a global power-down or standby functionality, as shown in Table 4.

9.4.4 Internal Dither Algorithm

The ADC344x family uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm may be turned off by using the DIS DITH CHx registers bits. Figure 155 and Figure 156 show the effect of using dither algorithms.

SFDR = 98 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS, THD = 97 dBc, HD2 = 110.0 dBc, HD3 = 98 dBc, SFDR = 100 dBc (excluding HD2, HD3)

Figure 155. FFT for 10-MHz Input Signal (Dither On)

SFDR = 90 dBc, SNR = 73.5 dBFS, SINAD = 73.2 dBFS, THD = 88 dBc, HD2 = 90 dBc, HD3 = 100 dBc, SFDR = 92 dBc (excluding HD2, HD3)

Figure 156. FFT for 10-MHz Input Signal (Dither Off)

9.4.5 Summary of Performance Mode Registers

Table 5 lists the location, value, and functions of performance mode registers in the device.

9.5.1 Serial Interface

The device has a set of internal registers that may be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data may be loaded in multiples of 24-bit words within a single active SEN pulse. The interface may function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 157. If required, the serial interface registers may be cleared during operation either:

1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) to high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register may be programmed with these steps:

1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 157 and Table 6 show the timing requirements for the serial register write operation.

Figure 157. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing⁽¹⁾

		MIN	TYP	MAX	UNIT
fSCLK	SCLK frequency (equal to 1 / tSCLK)	> DC		20	MHz
tSLOADS	SEN to SCLK setup time	25			ns
tSLOADH	SCLK to SEN hold time	25			ns
tDSU	SDIO setup time	25			ns
tDH	SDIO hold time	25			ns

(1) Typical values are at 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted.

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers may be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:

1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller may latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 158 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 159.

Figure 158. Serial Register Read Timing Diagram

Figure 159. SDOUT Timing Diagram

9.5.2 ADC3441 Power-Up Requirements

Power-up begins with the application of AVDD and DVDD. The exact sequencing and ramp rate of AVDD and DVDD are not important as long as the parameters in Table 7 are met.

After power-up, the RESET pin must be pulsed high to reset the internal registers to the default values. Figure 160 and Table 7 show a power-up sequence.

During operation, the device registers can be restored to the default values by either pulsing the RESET pin high or by issuing a software reset via the SPI interface. A software reset can be issued by writing bit 0 of register 06h high. This bit is self-clearing.

Figure 160. Power-Up Timing

After the power supplies are valid, enable the sample clock. The sampling clock can be enabled before or after reset, but conversions are not valid until at least a minimum time after reset and the time that the sample clock reaches a stable frequency, as shown in Table 7.

Before using samples from the device, a minimum register write sequence must be applied, as described in Table 8. Apply this register write sequence after any further application of the hardware or software reset.

These register writes configure the optimal settings for ADC performance and apply a reset to the internal latches inside the ADC core that are not part of the device reset function. After the register writes of Table 8 are written, any use-case-specific registers must be applied before using the conversion values.

Table 9. Register Map Summary

9.6.1 Serial Register Description