ZHCSQQ1B june 2022 – august 2023 ADC32RF54 , ADC32RF55
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
- 6.9 Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
- 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
- 6.11 Timing Requirements
- 6.12 Typical Characteristics - ADC32RF54
- 6.13 Typical Characteristics - ADC32RF55
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6
JESD204B Interface
- 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
- 7.3.6.2 JESD204B Frame Assembly
- 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
- 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
- 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
- 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
- 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
- 7.3.7 SERDES Output MUX
- 7.3.8 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Applications
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 STEP 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.5 Decimation Filter
The ADC32RF5x provides up to four digital down converters per ADC channel, see Figure 7-23. The decimation filters provide a flexible option to cover a wide range of instantaneous bandwidths (IBW) as shown in Table 7-15. Single band decimation supports a wide bandwidth up to complex decimation by 4x while up to four narrow band channels with up to 128x complex decimation are supported in quad band decimation mode.
Figure 7-23 Digital Decimation Filter Options| # of DDCs | Minimum Complex Decimation | Maximum Complex Decimation |
|---|---|---|
| 1 | 4 | 128 |
| 2 | 8 | 128 |
| 4 | 16 | 128 |
The decimation filter can be configured to two different operating modes:
- Complex Decimation: This mode provides complex output with ~ 80% passband bandwidth using a 48-bit phase coherent NCO.
During the complex mixing operation the digital output is reduced by 6-dB. This reduces the fullscale from 0-dBFS to -6-dBFS. This 6-dB change applies to signals and noise and thus no dynamic range is lost.
- Real Decimation: In real decimation mode, the complex mixer is bypassed (NCO is set to 0 for lowest power consumption), and the digital filter acts as a low pass filter. There is no frequency shifting and the output passband bandwidth is ~ 40%.
Since the JESD204B interface is common across ADC channel A and B, the decimation ratio as well as the # of DDCs/ADC has to be the same across channels A and B.
By default, the output of values of the decimation filter are rounded to 16-bit resolution. In order to avoid quantization noise limitation when using high order of decimation (that is /64 or /128), a special 20-bit output mode can be enabled (see 20-bit Output Mode).
Table 7-16 provides an overview of the available complex decimation settings and resulting complex and real output bandwidths.
| Decimation Factor N (complex) | Complex Output Bandwidth per DDC | FS = 3 Gsps | Real Output Bandwidth per DDC | FS = 3 Gsps | ||
|---|---|---|---|---|---|---|
| Complex Output Rate per DDC | Complex Output Bandwidth per DDC | Real Output Rate per DDC | Real Output Bandwidth per DDC | |||
| 4 | 0.8 x FS / 4 | 750 Msps | 600 MHz | 0.4 x FS / 4 | 750 Msps | 300 MHz |
| 8 | 0.8 x FS / 8 | 375 Msps | 300 MHz | 0.4 x FS / 8 | 375 Msps | 150 MHz |
| 16 | 0.8 x FS / 16 | 187.5 Msps | 150 MHz | 0.4 x FS / 16 | 187.5 Msps | 75 MHz |
| 32 | 0.8 x FS / 32 | 93.75 Msps | 75 MHz | 0.4 x FS / 32 | 93.75 Msps | 37.5 MHz |
| 64 | 0.8 x FS / 64 | 46.875 Msps | 37.5 MHz | 0.4 x FS / 64 | 46.875 Msps | 18.75 MHz |
| 128 | 0.8 x FS / 128 | 23.4375 Msps | 18.75 MHz | 0.4 x FS / 128 | 23.4375 Msps | 9.375 MHz |