ZHCSQQ1B june 2022 – august 2023 ADC32RF54 , ADC32RF55
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
- 6.9 Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
- 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
- 6.11 Timing Requirements
- 6.12 Typical Characteristics - ADC32RF54
- 6.13 Typical Characteristics - ADC32RF55
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6
JESD204B Interface
- 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
- 7.3.6.2 JESD204B Frame Assembly
- 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
- 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
- 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
- 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
- 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
- 7.3.7 SERDES Output MUX
- 7.3.8 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Applications
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 STEP 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
訂購信息
7.3.1.4 Analog out-of-band dither
The ADC32RF5x provides optional (enabled via SPI writes) analog out-of-band, large amplitude dither. It has a bandwidth of ~ 20 MHz located at DC and an adjustable amplitude with a maximum dither power of ~ -20 dBFS (PAR ~ 9 dB). The dither is completely rolled-off into the noise floor within ~ 100 MHz as illustrated in Figure 7-7. Since the dither is large amplitude, it is recommended for the signal input not to exceed -2.5 dBFS to avoid input saturation. The dither signal also couples to the input signal and, depending on input frequency, can degrade the close in phase noise.
Figure 7-7 Analog out-of-band ditherIn the frequency domain the dither signal shows up like individual tones as shown in Figure 7-12. The dither update frequency can be adjusted with the dither divider setting. The dither update frequency is: FS / 4 / 2047 / 'Dither Divider'. In the frequency spectrum there will be 2 larger dither spurs at FIN +/- FS / 4 / 'Dither Divider'.
By default, the divider is set to 50, which translates to a dither spur spacing of ~ 7 kHz. A divider setting of 32 translates to a dither spacing of ~ 11 kHz as shown in Figure 7-9. The lower the divider setting, the higher the dither tone frequency. Figure 7-9 also shows that the dither energy reduces as the offset frequency increases - less dither energy reduces the higher harmonic spur improvement.
Figure 7-8 Dither Close-Up
Figure 7-9 Dither vs Dither Divider SettingThe analog dither needs to be enabled in multiple locations. Different dither amplitudes should be used depending on internal averaging used as shown in Table 7-5.
| Mode | Amplitude | Dither Amp1 | Dither Amp2 |
|---|---|---|---|
| 1x AVG | +/-1024 codes | 0 | 0 |
| 1x AVG | +/-768 codes | 0 | -4 |
| 2x/4x AVG | +/-1024 codes | 3 | 0 |
| 2x/4x AVG | +/-768 codes | 0 | 0 |
The internal analog dither can be enabled via the following register writes. The dither divider is set in register 0xB1 as actual -1 (e.g. a divider of 48 would be programmed as 47, default is 0x00 which is divider = 50). See Table 7-9.
| ADDR | DATA | DESCRIPTION | ADDR | DATA | DESCRIPTION | |
|---|---|---|---|---|---|---|
| 0x05 | 0x40 | Select ANALOG page | 0xB1 | 0x00 |
Sets dither divider. 0x00 = /50 | |
| 0xA8 | 0x00 | DITHER AMP1: 3 = 0x80, 0 = 0x00 | 0xB2 | 0x00 | ||
| 0xCD | 0x00 | DITHER AMP2: -4 = 0x40, 0 = 0x00 | 0xAF | 0x18 | ||
| 0x04 | 0x01 | 0xAF | 0x10 | 0x10 = dither ENABLED, 0x90 = dither DISABLED | ||
| 0x20 | 0x04 | 0x04 | 0x01 | |||
| 0x91 | 0x40 | 0x20 | 0x00 | |||
| 0xAF | 0x10 | 0x04 | 0x00 |