4 Revision History

Changes from Revision C (July 2019) to Revision D (August 2019)

• Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Deleted Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go

Changes from Revision B (March 2016) to Revision C (July 2019)

• 在說明 中添加了文本：此外，還提供單線制串行 LVDS 接口。Go
• Changed the description of pin AVDD, DVDD, GND, and PDN pins in the Pin Functions table Go
• Changed the condition statement for Electrical Characteristics: General Go
• Moved the location of Electrical Characteristics: General Go
• Changed the parameter description of E_G(REF) in Electrical Characteristics: General Go
• Deleted E_G(CHAN) from Electrical Characteristics: General Go
• Changed the parameter description of α_(EGCHAN) in Electrical Characteristics: General Go
• Changed the condition statement for Electrical Characteristics: ADC3221, ADC3222 Go
• Changed ADC clock frequency (ADC3241) From: MAX = 125 MSPS To: MAX = 25 MSPS in Electrical Characteristics: ADC3221, ADC3222 Go
• Changed ADC clock frequency (ADC3242) From: MAX = 125 MSPS To: MAX = 50 MSPS in Electrical Characteristics: ADC3221, ADC3222 Go
• Changed the condition statement for Electrical Characteristics: ADC3223, ADC3224 Go
• Changed the condition statement for Electrical Characteristics: ADC3221 Go
• Changed the condition statement for Electrical Characteristics: ADC3222 Go
• Changed the condition statement for Electrical Characteristics: ADC3223 Go
• Changed the condition statement for Electrical Characteristics: ADC3224 Go
• Added Differential swing to DIGITAL INPUTS (SYSREFP, SYSREFM) Go
• Deleted V_IH and V_IL from DIGITAL INPUTS (SYSREFP, SYSREFM) Go
• added table note: SYSREF is internally biased to 0.9 V.to Digital Characteristics Go
• Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Added Graphs: Histogram, Integral Nonlinearity, and Differential Nonlinearity Go
• Changed the Overview sectionGo
• Added Using the SYSREF Input sectionGo
• Changed the Register Initialization through SPI sectionGo
• Changed the Detailed Design Procedure sectionGo

Changes from Revision A (March 2015) to Revision B (March 2016)

• Added Digital Inputs section to Digital Characteristics tableGo
• Changed Wake-up time parameter maximum specifications in Timing Requirements: General tableGo
• Updated Figure 6-19, Figure 6-20, Figure 6-23, Figure 6-24, Figure 6-25 and, Figure 6-26 Go
• Updated Figure 6-50, Figure 6-53, Figure 6-54, Figure 6-55, and Figure 6-56 Go
• Updated Figure 6-79, Figure 6-80, Figure 6-83, Figure 6-84, Figure 6-85, and Figure 6-86 Go
• Updated Figure 6-109, Figure 6-110, Figure 6-113, Figure 6-114, Figure 6-115, and Figure 6-116.Go
• Changed conditions of Figure 6-122 and Figure 6-124 Go
• Changed Figure 7-2 Go
• Changed SNR and Clock Jitter section: changed typical thermal noise value in description of and changed Figure 8-7 to reflect updated thermal noise value Go
• Changed Table 8-1 Go
• Changed Lane to Wire in Figure 8-8 Go
• Changed Register Map Summary table: changed FLIP BITS to FLIP WIRE in register 04h, changed bit 7 in register 70Ah, and added register 13hGo
• Changed Summary of Special Mode Registers section: changed title, moved section to correct locationGo
• Changed lane to wire in register 03h description Go
• Changed register 04h: changed FLIP BITS to FLIP WIRE and changed description of bit 0Go
• Changed register 0Ah and 0Bh descriptionsGo
• Added register 13hGo
• Changed register 70Ah to include the DIS CLK FILT register bitGo

Changes from Revision * (July 2014) to Revision A (March 2015)

• 已發布為“量產數據”Go