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ZHCSEU3E July 2014 – June 2022 ADC3221 , ADC3222 , ADC3223 , ADC3224

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND131R

訂購信息

6.14 Timing Requirements: LVDS Output

typical values are at T_A = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x serialization (2-wire mode), C_LOAD = 3.3 pF⁽²⁾, and R_LOAD = 100 Ω⁽³⁾ (unless otherwise noted); minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C⁽⁴⁾⁽¹⁾

			MIN	TYP	MAX	UNIT
t_SU	Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)⁽⁵⁾		0.43	0.5		ns
t_HO	Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid⁽⁵⁾		0.48	0.58		ns
t_PDI	Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over (15 MSPS < sampling frequency < 125 MSPS)	1-wire mode	2.7	4.5	6.5	ns
t_PDI		2-wire mode	0.44 × t_S + t_DELAY			ns
t_DELAY	Delay time		3	4.5	5.9	ns
	LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM)			49%
t_FALL, t_RISE	Data fall time, data rise time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS			0.11		ns
t_CLKRISE, t_CLKFALL	Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV, 10 MSPS ≤ Sampling frequency ≤ 125 MSPS			0.11		ns

(1) Timing parameters are specified by design and characterization and are not tested in production.

(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.

(3) R_LOAD is the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(5) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.

Table 6-1 LVDS Timing at Lower Sampling Frequencies: 6X Serialization (2-Wire Mode)

SAMPLING FREQUENCY (MSPS)	SETUP TIME (t_SU, ns)			HOLD TIME (t_HO, ns)
SAMPLING FREQUENCY (MSPS)	MIN	TYP	MAX	MIN	TYP	MAX
25	2.61	3.06		2.75	3.12
40	1.69	1.9		1.8	1.98
60	1.11	1.23		1.18	1.31
80	0.81	0.89		0.88	0.97
100	0.6	0.68		0.68	0.77

Table 6-2 LVDS Timings at Lower Sampling Frequencies: 12X Serialization (1-Wire Mode)

SAMPLING FREQUENCY (MSPS)	SETUP TIME (t_SU, ns)			HOLD TIME (t_HO, ns)
SAMPLING FREQUENCY (MSPS)	MIN	TYP	MAX	MIN	TYP	MAX
25	1.3	1.48		1.32	1.57
40	0.76	0.88		0.79	0.97
50	0.57	0.68		0.61	0.77
60	0.42	0.55		0.45	0.62
70	0.35	0.44		0.4	0.51
80	0.26	0.35		0.35	0.43