ZHCSUL6 February 2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DEVICE (SAMPLING) CLOCK (CLK+, CLK–) | ||||||
| tAD | Sampling (aperture) delay from CLK± rising edge (dual channel mode) or rising and falling edge (single channel mode) to sampling instant(4) | TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0 | 360 | ps | ||
| tAD(MAX) | Maximum tAD Adjust programmable delay, not including clock inversion (TAD_INV = 0) | Coarse adjustment (TAD_COARSE = 0xFF) | 289 | ps | ||
| Fine adjustment (TAD_FINE = 0xFF) | 4.9 | |||||
| tAD(STEP) | Aperture delay step size | Coarse adjustment (TAD_COARSE) | 1.13 | ps | ||
| Fine adjustment (TAD_FINE) | 19 | fs | ||||
| tAJ | Aperture jitter, rms | Minimum tAD Adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) | 55 | fs | ||
| Minimum tAD Adjust coarse setting (TAD_COARSE = 0xFF, TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) | 70 | |||||
| Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) | 70(1) | |||||
| Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) | 80(1) | |||||
| LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±) | ||||||
| fBIT | Output bit rate per output data pair | 1.6 | Gbps | |||
| fDCLK | DDR data clock frequency | 800 | MHz | |||
| tDJ | DDR data clock total jitter, peak-to-peak, with random jitter portion defined with respect to a BER=1e–15 (Q=7.94) | UPAT_CTRL = 0x10 | 36 | ps | ||
| tSKEW(SAME) | Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) within the same LVDS bank over operating conditions | 75 | ps | |||
| tSKEW(ALL) | Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) in all LVDS banks over operating conditions with tOSAB, tOSAC and tOSBD skew excluded | 125 | ps | |||
| tOSAB | Functional timing offset between DACLK± rising edge and DBCLK± rising edge, positive number indicates that DACLK± leads DBCLK± | DES_EN = 0, LDEMUX = 0, LALIGNED = 0 | 0 | tCLK | ||
| DES_EN = 0, LDEMUX = 0, LALIGNED = 1 | 0 | |||||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 0 | 0 | |||||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 1 | 0 | |||||
| DES_EN = 1, LDEMUX = 0, LALIGNED = 0 | 0.5 | |||||
| DES_EN = 1, LDEMUX = 0, LALIGNED = 1 | 0 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 0 | 0.5 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 1 | 0 | |||||
| tOSAC | Functional timing offset between DACLK± rising edge and DCCLK± rising edge, positive number indicates that DACLK± leads DCCLK± | DES_EN = 0, LDEMUX = 1, LALIGNED = 0 | 1 | tCLK | ||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 1 | 0 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 0 | 1 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 1 | 0 | |||||
| tOSBD | Functional timing offset between DBCLK± rising edge and DDCLK± rising edge, positive number indicates that DBCLK± leads DDCLK± | DES_EN = 0, LDEMUX = 1, LALIGNED = 0 | 1 | tCLK | ||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 1 | 0 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 0 | 1 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 1 | 0 | |||||
| tTLH | Low-to-high transition time (differential) | 20% to 80%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10 | 125 | ps | ||
| 20% to 80%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10 | 200 | |||||
| tTHL | High-to-low transition time (differential) | 80% to 20%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10 | 125 | ps | ||
| 80% to 20%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10 | 200 | |||||
| LATENCY | ||||||
| tOD | Output delay from CLK± rising edge (dual-channel mode) or falling edge (single-channel mode) to DACLK± output(4) | TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0 | 1.5 | ns | ||
| tLAT(DIG) | CLK± edge that samples input signal to CLK± edge that launches data, digital latency only(2)(4) | DES_EN = 0, LDEMUX = 0, LALIGNED = 0 | 26 | tCLK | ||
| DES_EN = 0, LDEMUX = 0, LALIGNED = 1 | 26 | |||||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 0 | 26 | |||||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 1 | 27 | |||||
| DES_EN = 1, LDEMUX = 0, LALIGNED = 0 | 26 | |||||
| DES_EN = 1, LDEMUX = 0, LALIGNED = 1 | 26.5 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 0 | 26 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 1 | 27.5 | |||||
| tLAT(STB) | Latency from SYSREF± being sampled by rising edge of CLK± to the start of the corresponding data frame(3) | DES_EN = 0, LDEMUX = 0, LALIGNED = 0 | 47 | tCLK | ||
| DES_EN = 0, LDEMUX = 0, LALIGNED = 1 | 47 | |||||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 0 | 47 | |||||
| DES_EN = 0, LDEMUX = 1, LALIGNED = 1 | 48 | |||||
| DES_EN = 1, LDEMUX = 0, LALIGNED = 0 | 46.5 | |||||
| DES_EN = 1, LDEMUX = 0, LALIGNED = 1 | 47 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 0 | 46.5 | |||||
| DES_EN = 1, LDEMUX = 1, LALIGNED = 1 | 48 | |||||
| tLAT(SYNCSE) | Latency from SYNCSE assertion or deassertion to DB0± (LSB) changing from normal data to strobe output or strobe output to normal data, digital latency only | LDEMUX = 0 | 26 | 36+1*LFRAME | tCLK | |
| LDEMUX = 1 | 26 | 36+2*LFRAME | ||||
| SERIAL PROGRAMMING INTERFACE (SDO) | ||||||
| t(OZD) | Delay from falling edge of 16th SCLK cycle during read operation for SDO transition from tri-state to valid data | 1 | ns | |||
| t(ODZ) | Delay from SCS rising edge for SDO to transition from valid data to tri-state | 10 | ns | |||
| t(OD) | Delay from falling edge of SCLK during read operation to SDO valid | 1 | 10 | ns | ||