ZHCSON8A July 2021 – October 2024 ADC09DJ800-Q1 , ADC09QJ800-Q1 , ADC09SJ800-Q1
PRODUCTION DATA
ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle codes, resulting from meta-stability caused by non-ideal comparator limitations. The device uses a unique ADC architecture that inherently allows significant code error rate improvements from traditional pipelined flash or successive approximation register (SAR) ADCs. The code error rate of the device is multiple orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing significant signal reliability improvements.