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ZHCSOS8A October 2021 – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

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封裝選項

機械數據 (封裝 | 引腳)

AAV|144
- MPBGAM2C

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

5.5 Electrical Characteristics: DC Specifications

typical values at T_A = 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (V_FS = 0.8 V_PP), f_IN = 97 MHz, A_IN = –1 dBFS, f_CLK = 1.3 GHz, filtered 1-V_PP sine-wave clock applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC ACCURACY
	Resolution	Resolution with no missing codes		9		Bits
DNL	Differential nonlinearity	Maximum positive excursion from ideal step size		0.16		LSB
DNL	Differential nonlinearity	Maximum negative excursion from ideal step size		–0.15		LSB
INL	Integral nonlinearity	Maximum positive excursion from ideal transfer function		0.33		LSB
INL	Integral nonlinearity	Maximum negative excursion from ideal transfer function		–0.3		LSB
ANALOG INPUTS (INA+, INA–, INB+, INB–, INC+, INC–, IND+, IND–)
V_OFF	Offset error	CAL_OS = 0		±0.4		mV
V_OFF	Offset error	CAL_OS = 1		±0.4		mV
V_{OFF_ADJ}	Input offset voltage adjustment range	Available offset correction range (see OFSx or OFSxCh registers)		±33		mV
V_{OFF_DRIFT}	Offset drift	Foreground calibration at nominal temperature only, CAL_OS = 1		-1.2		μV/°C
V_{OFF_DRIFT}	Offset drift	Foreground calibration at each temperature, CAL_OS = 1		0.25		μV/°C
V_FS	Analog differential input full-scale range	Default full-scale voltage (FS_RANGE = 0xA000), measured at DC	750	800	850	mV_PP
		Maximum full-scale voltage (FS_RANGE = 0xFFFF), measured at DC	980	1040
		Minimum full-scale voltage (FS_RANGE = 0x2000), measured at DC		480	500
V_{FS_DRIFT}	Analog differential input full-scale range drift	Default FS_RANGE setting, foreground calibration at nominal temperature only, inputs driven by a 50-Ω source, includes effect of R_IN drift		–0.0015		%/°C
V_{FS_DRIFT}	Analog differential input full-scale range drift	Default FS_RANGE setting, foreground calibration at each temperature, inputs driven by a 50-Ω source, includes effect of R_IN drift		-.000018		%/°C
V_{FS_MATCH}	Analog differential input full-scale range matching	Matching between any two channels (e.g. INA± and INB±), default full-scale voltage, measured at DC		1%
R_IN	Differential input resistance	Center of differential resistance is terminated to V_CM, measured at T_A = 25°C	92	100	108	Ω
R_{IN_TEMPCO}	Input termination linear temperature coefficient			38		mΩ/°C
C_IN	Single-ended input capacitance	Measured at DC		0.6		pF
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
ΔV_BE	Temperature diode voltage slope	Forced forward current of 100 μA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement must be done with the device unpowered or with the PD pin asserted to minimize device self-heating.		–1.6		mV/°C
BAND-GAP VOLTAGE OUTPUT (BG)
V_BG	Internal band-gap reference and V_CM reference output voltage	I_L ≤ 100 μA		1.1		V
V_{BG_DRIFT}	V_BG output temperature drift	I_L ≤ 100 μA		–117		μV/°C
DIFFERENTIAL CLOCK AND TIMESTAMP INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
Z_T	Internal termination	Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0		100		Ω
Z_T	Internal termination	Single-ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0		50		Ω
V_CM	Input common-mode voltage, self-biased	Self-biasing common-mode voltage for CLK± when AC-coupled (DEVCLK_LVPECL_EN must be set to 0)		0.3		V
		Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1)		0.3
		Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0)		VA11
C_{L_DIFF}	Differential input capacitance	Between positive and negative differential input pins		0.1		pF
C_{L_SE}	Single-ended input capacitance	Each input to ground		0.5		pF
CLOCK AND TRIGGER OUTPUTS (PLLREFO+, PLLREFO–, TRIGOUT+, TRIGOUT–)
V_DIFF	Differential output voltage, peak-to-peak, DC measurement	100-Ω load	400	720	900	mV_PP-DIFF
V_CM(PLLREFO)	PLLREFO± output common-mode voltage			1.31⁽¹⁾		V
V_CM(TRIGOUT)	TRIGOUT± output common-mode voltage, tracks with VTRIG	VTRIG = 1.9		1.31⁽²⁾		V
V_CM(TRIGOUT)	TRIGOUT± output common-mode voltage, tracks with VTRIG	VTRIG = 1.1		0.5⁽²⁾		V
Z_DIFF	Differential output impedance	Measured at DC		300		?
SERDES OUTPUTS (D[7:0]+, D[7:0]–)
V_OD	Differential output voltage, peak-to-peak	100-Ω load		600		mV_PP-DIFF
V_CM	Output common-mode voltage	AC coupled		0.54		V
Z_DIFF	Differential output impedance			100		Ω
CMOS INTERFACE (SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, CLKCFG0, CLKCFG1, PLL_EN, PLLREF_SE, ORA, ORB, ORC, ORD, SYNCSE)
V_IH	High-level input voltage		0.7			V
V_IL	Low-level input voltage				0.45	V
I_IH	High-level input current				40	μA
I_IL	Low-level input current		–40			μA
C_I	Input capacitance			2		pF
V_OH	High-level output voltage	I_LOAD = –400 μA	1.65			V
V_OL	Low-level output voltage	I_LOAD = 400 μA			150	mV

(1) TI recommends AC-coupling PLLREFO± to the load device when PLLREFO± is enabled.

(2) TI recommends AC-couping TRIGOUT± to the load device when TRIGOUT± is enabled and used as a clock output (from S-PLL). TRIGOUT± can be DC-coupled to the load device when TRIGOUT± is used as a trigger output (from TMSTP±).