ZHCSOS8A October 2021 – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300
PRODUCTION DATA
The transport layer takes samples from the ADC output and maps the samples into octets inside of frames. These frames are then mapped onto the available lanes. The mapping of octets into frames and frames onto lanes is defined by the transport layer settings such as L, M, F, S, N and N'. An octet is 8 bits (before 8B/10B or 64B/66B encoding), a frame consists of F octets and the frames are mapped onto L lanes. Samples are N bits, but sent as N' bits across the link. The samples come from M converters and there are S samples per converter per frame cycle. M is sometimes artificially increased in order to obtain a more desirable mapping, for instance lower latency may be achieved with a larger M value for long frames.
There are a number of predefined transport layer modes in the device that are defined in Table 6-16, Table 6-17 and Table 6-18. The high level configuration parameters for the transport layer in the device are described in Table 6-14. The transport layer mode is chosen by simply setting the JMODE register setting. For reference, the various configuration parameters for JESD204C are defined in Table 6-15.
The link layer further maps the frames into multiframes when using 8B/10B encoding or blocks, multiblocks and extended multiblocks when using 64B/66B encoding.