ZHCSN42B August 2021 – April 2025 ADC08DJ5200RF
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics: DC Specifications
- 5.6 Electrical Characteristics: Power Consumption
- 5.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)
- 5.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)
- 5.9 Timing Requirements
- 5.10 Switching Characteristics
- 5.11 Typical Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Device Comparison
- 6.3.2 Analog Inputs
- 6.3.3 ADC Core
- 6.3.4 Temperature Monitoring Diode
- 6.3.5 Timestamp
- 6.3.6 Clocking
- 6.3.7 Programmable FIR Filter (PFIR)
- 6.3.8
JESD204C Interface
- 6.3.8.1 Transport Layer
- 6.3.8.2 Scrambler
- 6.3.8.3 Link Layer
- 6.3.8.4 8B/10B Link Layer
- 6.3.8.5
64B/66B Link Layer
- 6.3.8.5.1 64B/66B Encoding
- 6.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
- 6.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
- 6.3.8.5.4 Initial Lane Alignment
- 6.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
- 6.3.8.6 Physical Layer
- 6.3.8.7 JESD204C Enable
- 6.3.8.8 Multi-Device Synchronization and Deterministic Latency
- 6.3.8.9 Operation in Subclass 0 Systems
- 6.3.9 Alarm Monitoring
- 6.4
Device Functional Modes
- 6.4.1 Dual-Channel Mode
- 6.4.2 Single-Channel Mode (DES Mode)
- 6.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
- 6.4.4 JESD204C Modes
- 6.4.5 Power-Down Modes
- 6.4.6 Test Modes
- 6.4.7 Calibration Modes and Trimming
- 6.4.8 Offset Calibration
- 6.4.9 Trimming
- 6.5 Programming
- 6.6 SPI Register Map
- 7 Application Information Disclaimer
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- AAV|144
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
3 說(shuō)明
ADC08DJ5200RF 器件是一款射頻采樣千兆采樣模數(shù)轉(zhuǎn)換器 (ADC)，可對(duì)從直流到 10GHz 以上的輸入頻率進(jìn)行直接采樣。ADC08DJ5200RF 可配置為雙通道 5.2GSPS ADC 或單通道 10.4GSPS ADC。支持高達(dá) 10GHz 的可用輸入頻率范圍，可對(duì)頻率捷變系統(tǒng)的 L、S、C 和 X 頻帶進(jìn)行直接射頻采樣。
ADC08DJ5200RF 使用具有多達(dá) 16 個(gè)串行通道的高速 JESD204C 輸出接口，支持高達(dá) 17.16Gbps 的線路速率。通過(guò) JESD204C 子類 1 支持確定性延遲和多器件同步。JESD204C 接口可進(jìn)行配置，對(duì)線路速率和通道數(shù)進(jìn)行權(quán)衡。支持 8b/10b 和 64b/66b 數(shù)據(jù)編碼方案。64b/66b 編碼支持前向糾錯(cuò) (FEC)，可改進(jìn)誤碼率。此接口向后兼容 JESD204B 接收器。
無(wú)噪聲孔徑延遲調(diào)節(jié)和 SYSREF 窗口等創(chuàng)新的同步特性可簡(jiǎn)化多通道應(yīng)用的系統(tǒng)設(shè)計(jì)。可編程 FIR 濾波器可實(shí)現(xiàn)片上均衡。
(1) 有關(guān)所有可用封裝，請(qǐng)參閱 節(jié) 10。
(2) 封裝尺寸（長(zhǎng) × 寬）為標(biāo)稱值，并包括引腳（如適用）。
ADC08DJ5200RF 方框圖