The TPS70175 is designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS70175 ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution.

The TPS70175 voltage regulator offers low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors.

This device has a fixed 5 V/2.5 V voltage option. Regulator 1 can support up to 500 mA and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 280 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at T_J = 25°C.

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the V_SENSE1 and V_SENSE2 pins, respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, V_OUT2 turns on first and V_OUT1 remains off until V_OUT2 reaches approximately 83% of its regulated output voltage. At that time V_OUT1 is turned on. If V_OUT2 is pulled below 83% (for example, an overload condition), V_OUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and V_OUT1 is turned on first. The SEQ pin is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at V_OUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1.

The TPS70175 features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of V_OUT2 and both manual reset pins (MR1 and MR2). When V_OUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 30-ms delay. RESET goes to the logic low state when the V_OUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor V_OUT1, the PG1 output pin can be connected to MR1 or MR2.

The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on until V_IN1 reaches 2.5 V.