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TPS51100

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3A 拉電流/灌電流 DDR 終端器穩(wěn)壓器

產(chǎn)品詳情

Product type DDR Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.5 DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
Product type DDR Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.5 DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
HVSSOP (DGQ) 10 14.7 mm2 3 x 4.9
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.
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頂層文檔 類型 標題 格式選項 下載最新的英語版本 日期
* 數(shù)據(jù)表 TPS51100 3-A Sink / Source DDR Termination Regulator 數(shù)據(jù)表 (Rev. E) PDF | HTML 2014年 12月 17日
應(yīng)用手冊 LDO 噪聲揭秘 (Rev. B) PDF | HTML 英語版 (Rev.B) PDF | HTML 2020年 9月 16日
應(yīng)用手冊 DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日
選擇指南 電源管理指南 2018 (Rev. K) 2018年 7月 31日
選擇指南 電源管理指南 2018 (Rev. R) 2018年 6月 25日
應(yīng)用手冊 LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
應(yīng)用手冊 簡化的 LDO PSRR 測量 最新英語版本 (Rev.A) PDF | HTML 2010年 7月 28日
用戶指南 Using the TPS51100 2004年 7月 13日

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用戶指南: PDF
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仿真模型

TPS51100 PSpice Model

SLVC176.ZIP (473 KB) - PSpice Model
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仿真模型

TPS51100 TINA-TI Average Reference Design

SLVC203.ZIP (217 KB) - TINA-TI Reference Design
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仿真模型

TPS51100 TINA-TI Average Sink Reference Design (Rev. A)

SLVC177A.ZIP (217 KB) - TINA-TI Reference Design
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仿真模型

TPS51100 TINA-TI Average Spice Model

SLVC204.ZIP (7 KB) - TINA-TI Spice Model
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仿真模型

TPS51100 TINA-TI Transient Reference Design

SLVC206.ZIP (216 KB) - TINA-TI Reference Design
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仿真模型

TPS51100 TINA-TI Transient Spice Model

SLVC205.ZIP (7 KB) - TINA-TI Spice Model
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HVSSOP (DGQ) 10 Ultra Librarian

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  • MTBF/時基故障估算
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