• Dynamic Range with –60dB Input (A-Weighted): 144dB typical
• Total Harmonic Distortion and Noise (THD+N) with Full-Scale Input: –140dB typical
• Supports Audio Input and Output Data Word Lengths Up to 24 Bits
• Supports Input and Output Sampling Frequencies Up to 216kHz
• Automatic Detection of the Input-to-Output Sampling Ratio
• Wide Input-to-Output Conversion Range:
  16:1 to 1:16 Continuous
• Excellent Jitter Attenuation Characteristics
• Digital De-Emphasis Filtering for 32kHz, 44.1kHz, and 48kHz Input Sampling Rates
• Digital Output Attenuation and Mute Functions
• Output Word Length Reduction
• Status Registers and Interrupt Generation for Sampling Ratio and Ready Flags

• Supports Sampling Rates Up to 216kHz
• Includes Differential Line Driver and
  CMOS Buffered Outputs
• Block-Sized Data Buffers for Both Channel Status and User Data
• Status Registers and Interrupt Generation for Flag and Error Conditions

• Provides Access to On-Chip Registers and Data Buffers

U.S. Patent No. 7,262,716

• PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz
• Includes Four Differential Input Line Receivers and an Input Multiplexer
• Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
• Block-Sized Data Buffers for Both Channel Status and User Data
• Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
• Audio CD Q-Channel Sub-Code Decoding and Data Buffer
• Status Registers and Interrupt Generation for Flag and Error Conditions
• Low Jitter Recovered Clock Output

• Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
• Slave or Master Mode Operation with Sampling Rates up to 216kHz
• Supports Left-Justified, Right-Justified, and Philips I²S? Data Formats
• Supports Audio Data Word Lengths Up to
  24 Bits

• Multifunction Programmable Via Control Registers

• Functional Blocks May Be Disabled Individually When Not In Use

• QFN-40
• Small TQFP-48 Package, Compatible with the SRC4382 and DIX4192