SN74LVTH16543-EP

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具有三態(tài)輸出的增強(qiáng)型產(chǎn)品 3.3V ABT 16 位寄存收發(fā)器

產(chǎn)品詳情

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 64 IOH (max) (mA) -64 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVT Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 64 IOH (max) (mA) -64 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVT Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SSOP (DL) 56 190.647 mm2 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm2 14 x 8.1
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product–Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus? Family
  • State–of–the–Art Advanced BiCMOS Technology (ABT) Design for 3.3–V Operation and Low Static–Power Dissipation
  • Supports Mixed–Mode Signal Operation (5–V Input and Output Voltages With 3.3–V VCC)
  • Supports Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power–Up 3–State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Distributed VCC and GND Pins Minimize High–Speed Switching Noise
  • Flow–Through Architecture Optimizes PCB Layout
  • Latch–Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL–STD–883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Widebus Is a trademark of Texas Instruments
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product–Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus? Family
  • State–of–the–Art Advanced BiCMOS Technology (ABT) Design for 3.3–V Operation and Low Static–Power Dissipation
  • Supports Mixed–Mode Signal Operation (5–V Input and Output Voltages With 3.3–V VCC)
  • Supports Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power–Up 3–State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Distributed VCC and GND Pins Minimize High–Speed Switching Noise
  • Flow–Through Architecture Optimizes PCB Layout
  • Latch–Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL–STD–883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Widebus Is a trademark of Texas Instruments

The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCC operation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEAB or LEBA) and output–enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A–to–B latches are transparent; a subsequent low–to–high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs.

Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver.

This device is fully specified for hot–insertion applications using Ioff and power–up 3–state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCC operation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEAB or LEBA) and output–enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A–to–B latches are transparent; a subsequent low–to–high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs.

Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver.

This device is fully specified for hot–insertion applications using Ioff and power–up 3–state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.
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頂層文檔 類型 標(biāo)題 格式選項(xiàng) 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 SN74LVTH16543-EP 數(shù)據(jù)表 (Rev. B) 2006年 6月 16日
* VID SN74LVTH16543-EP VID V6204715 2016年 6月 21日
* 輻射與可靠性報(bào)告 CLVTH16543IDGGREP Reliability Report 2014年 12月 22日
* 輻射與可靠性報(bào)告 CLVTH16543MDLREP Reliability Report 2014年 12月 22日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
應(yīng)用手冊(cè) 慢速或浮點(diǎn) CMOS 輸入的影響 (Rev. E) PDF | HTML 英語(yǔ)版 (Rev.E) 2025年 3月 26日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語(yǔ)版本 (Rev.AC) PDF | HTML 2014年 11月 17日
選擇指南 《高級(jí)總線接口邏輯器件選擇指南》 英語(yǔ)版 2010年 7月 7日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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應(yīng)用手冊(cè) Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
應(yīng)用手冊(cè) LVT-to-LVTH Conversion 1998年 12月 8日
應(yīng)用手冊(cè) LVT Family Characteristics (Rev. A) 1998年 3月 1日
應(yīng)用手冊(cè) Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應(yīng)用手冊(cè) Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
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