產品詳情

Bits (#) 19 Data rate (max) (Mbps) 150 Topology Open drain Direction control (typ) Direction-controlled Vin (min) (V) 1.6, 4.5 Vin (max) (V) 5.5 Vout (min) (V) 4.5 Vout (max) (V) 5.5 Applications IEEE1284 Features Output enable, Partial power down (Ioff) Prop delay (ns) 30 Technology family LV-A Supply current (max) (mA) 70 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 19 Data rate (max) (Mbps) 150 Topology Open drain Direction control (typ) Direction-controlled Vin (min) (V) 1.6, 4.5 Vin (max) (V) 5.5 Vout (min) (V) 4.5 Vout (max) (V) 5.5 Applications IEEE1284 Features Output enable, Partial power down (Ioff) Prop delay (ns) 30 Technology family LV-A Supply current (max) (mA) 70 Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm2 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm2 12.5 x 8.1
  • 4.5-V to 5.5-V VCC Operation
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JEDEC 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 300-V Machine Model (A115-A)
    • 2000-V Charged-Device Model (C101)
  • 4.5-V to 5.5-V VCC Operation
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JEDEC 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 300-V Machine Model (A115-A)
    • 2000-V Charged-Device Model (C101)

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
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類型 標題 下載最新的英語版本 日期
* 數據表 SN74LV161284 數據表 (Rev. C) 2002年 11月 4日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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