SN74LS175

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具有清零功能的四通道 D 類觸發(fā)器

產品詳情

Number of channels 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 35 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (μA) 18000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 35 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (μA) 18000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm2 19.3 x 9.4 SOIC (D) 16 59.4 mm2 9.9 x 6 SOP (NS) 16 79.56 mm2 10.2 x 7.8
  • '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
  • '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
  • Three Performance Ranges Offered: See Table Lower Right
  • Buffered Clock and Direct Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Applications include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
  • '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
  • Three Performance Ranges Offered: See Table Lower Right
  • Buffered Clock and Direct Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Applications include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.
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類型 標題 下載最新的英語版本 日期
* 數據表 Hex/Quadruple D-Type Flip-Flops With Clear 數據表 (Rev. A) 2001年 10月 12日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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