SN74HC165
- Wide Operating Voltage Range of 2 V to 6 V
- Outputs Can Drive Up to 10 LSTTL Loads
- Low Power Consumption, 80-μA Maximum ICC
- Typical tpd = 13 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1 μA Maximum
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
- On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
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14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產(chǎn)品通用評估模塊
14-24-LOGIC-EVM 評估模塊 (EVM) 設(shè)計用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| SSOP (DB) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購和質(zhì)量
- RoHS
- REACH
- 器件標識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點
- 封裝廠地點