SN74F299

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通用移位/存儲寄存器

產(chǎn)品詳情

Configuration Universal Bits (#) 8 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 24 IOH (max) (mA) -3 Supply current (max) (μA) 95000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 8 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 24 IOH (max) (mA) -3 Supply current (max) (μA) 95000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm2 24.33 x 9.4 SOIC (DW) 20 131.84 mm2 12.8 x 10.3
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operates With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operates With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.
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類型 標題 下載最新的英語版本 日期
* 數(shù)據(jù)表 SN54F299, SN74F299 數(shù)據(jù)表 (Rev. B) 2004年 4月 16日
應用手冊 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
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選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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應用手冊 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發(fā)

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評估板

14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產(chǎn)品通用評估模塊

14-24-LOGIC-EVM 評估模塊 (EVM) 設計用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語版 (Rev.B): PDF | HTML
TI.com 上無現(xiàn)貨
封裝 引腳 CAD 符號、封裝和 3D 模型
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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