產品詳情

Number of channels 4 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (μA) 34000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 4 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (μA) 34000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm2 19.3 x 9.4 SOIC (D) 16 59.4 mm2 9.9 x 6 SOP (NS) 16 79.56 mm2 10.2 x 7.8
  • Contains Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Contains Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
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類型 標題 下載最新的英語版本 日期
* 數據表 Quadruple D-Type Flip-Flop With Clear 數據表 (Rev. B) 2002年 5月 22日

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓