產品詳情

Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 100 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 13 OFF-state leakage current (max) (μA) 10 Ron (max) (mΩ) 9500 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 24 Bandwidth (MHz) 100 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 13 OFF-state leakage current (max) (μA) 10 Ron (max) (mΩ) 9500 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
SSOP (DL) 56 190.647 mm2 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm2 14 x 8.1 TVSOP (DGV) 56 72.32 mm2 11.3 x 6.4
  • Member of the Texas Instruments Widebus Family
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on
    All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level
      Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output
      Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up
    or Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes
    Loading (Cio(OFF) = 5 pF Typ)
  • Data and Control Inputs Provide
    Undershoot Clamp Diodes
  • Low Power Consumption
    (ICC = 70 μA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL
    or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level
    Translation, PCI Interface, Bus Isolation
  • Ideal for Low-Power Portable Equipment
  • Member of the Texas Instruments Widebus Family
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on
    All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level
      Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output
      Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up
    or Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes
    Loading (Cio(OFF) = 5 pF Typ)
  • Data and Control Inputs Provide
    Undershoot Clamp Diodes
  • Low Power Consumption
    (ICC = 70 μA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL
    or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level
    Translation, PCI Interface, Bus Isolation
  • Ideal for Low-Power Portable Equipment

The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground.

The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground.

The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標題 下載最新的英語版本 日期
* 數據表 SN74CB3T16211 數據表 (Rev. C) 2012年 8月 17日
應用手冊 選擇正確的德州儀器 (TI) 信號開關 (Rev. E) PDF | HTML 英語版 (Rev.E) PDF | HTML 2022年 8月 5日
應用手冊 CBT-C、CB3T 和 CB3Q 信號開關系列 (Rev. C) PDF | HTML 英語版 (Rev.C) PDF | HTML 2022年 3月 11日
應用手冊 多路復用器和信號開關詞匯表 (Rev. B) 英語版 (Rev.B) PDF | HTML 2022年 3月 11日
應用簡報 利用關斷保護信號開關消除電源時序 (Rev. C) 英語版 (Rev.C) PDF | HTML 2021年 10月 21日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應用手冊 How to Select Little Logic (Rev. A) 2016年 7月 26日
應用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應用手冊 選擇正確的電平轉換解決方案 (Rev. A) 英語版 (Rev.A) 2006年 3月 23日
更多文獻資料 Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
應用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應用手冊 Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發

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仿真模型

HSPICE Model for SN74CB3T16211

SCDJ036.ZIP (118 KB) - HSpice Model
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仿真模型

SN74CB3T16211 IBIS Model

SCDM096.ZIP (28 KB) - IBIS Model
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封裝 引腳 CAD 符號、封裝和 3D 模型
SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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