產品詳情

Protocols Analog, I2C, UART Configuration 1:1 SPST Number of channels 2 Bandwidth (MHz) 500 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 4000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (μA) 700 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 8 OFF-state leakage current (max) (μA) 1 Ron (max) (mΩ) 9000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog, I2C, UART Configuration 1:1 SPST Number of channels 2 Bandwidth (MHz) 500 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 4000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (μA) 700 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 8 OFF-state leakage current (max) (μA) 1 Ron (max) (mΩ) 9000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
TSSOP (PW) 8 19.2 mm2 3 x 6.4 VSSOP (DCU) 8 6.2 mm2 2 x 3.1
  • High-Bandwidth Data Path (up to 500 MHz(1))
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Low and Flat ON-State Resistance (ron) Characteristics Over
    Operating Range (ron = 4 Ω Typ)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0- to 5-V Switching With 3.3-V VCC
    • 0- to 3.3-V Switching With 2.5-V VCC
    • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion
    (Cio(OFF) = 3.5 pF Typ)
  • Fast Switching Frequency (f OE = 20 MHz Max)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 0.25 mA Typ)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Differential Signal
    Interface, Bus Isolation, Low-Distortion Signal Gating

(1) For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.
  • High-Bandwidth Data Path (up to 500 MHz(1))
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Low and Flat ON-State Resistance (ron) Characteristics Over
    Operating Range (ron = 4 Ω Typ)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0- to 5-V Switching With 3.3-V VCC
    • 0- to 3.3-V Switching With 2.5-V VCC
    • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion
    (Cio(OFF) = 3.5 pF Typ)
  • Fast Switching Frequency (f OE = 20 MHz Max)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 0.25 mA Typ)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Differential Signal
    Interface, Bus Isolation, Low-Distortion Signal Gating

(1) For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.

The SN74CB3Q3306A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3306A is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3Q3306A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3306A is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技術文檔

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類型 標題 下載最新的英語版本 日期
* 數據表 SN74CB3Q3306A 數據表 (Rev. E) 2011年 1月 25日
應用手冊 選擇正確的德州儀器 (TI) 信號開關 (Rev. E) PDF | HTML 英語版 (Rev.E) PDF | HTML 2022年 8月 5日
應用手冊 CBT-C、CB3T 和 CB3Q 信號開關系列 (Rev. C) PDF | HTML 英語版 (Rev.C) PDF | HTML 2022年 3月 11日
應用手冊 多路復用器和信號開關詞匯表 (Rev. B) 英語版 (Rev.B) PDF | HTML 2022年 3月 11日
應用簡報 利用關斷保護信號開關消除電源時序 (Rev. C) 英語版 (Rev.C) PDF | HTML 2021年 10月 21日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
更多文獻資料 Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
應用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應用手冊 Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發

如需其他信息或資源，請點擊以下任一標題進入詳情頁面查看（如有）。

評估板

DIP-ADAPTER-EVM — DIP 適配器評估模塊

借助 DIP-Adapter-EVM 加快運算放大器的原型設計和測試，該 EVM 有助于快速輕松地連接小型表面貼裝 IC 并且價格低廉。您可以使用隨附的 Samtec 端子板連接任何受支持的運算放大器，或者將這些端子板直接連接至現有電路。

DIP-Adapter-EVM 套件支持六種常用的業界通用封裝，包括：

  • D 和 U (SOIC-8)
  • PW (TSSOP-8)
  • DGK（MSOP-8、VSSOP-8）
  • DBV（SOT23-6、SOT23-5 和 SOT23-3）
  • DCK（SC70-6 和 SC70-5）
  • DRL (SOT563-6)
用戶指南: PDF
TI.com 上無現貨
接口適配器

LEADED-ADAPTER1 — 表面貼裝轉 DIP 接頭適配器，用于快速測試 TI 的 5、8、10、16 和 24 引腳引線式封裝。

EVM-LEADED1 電路板可用于對 TI 的常見引線式封裝進行快速測試和電路板試驗。? 該電路板具有足夠的空間，可將 TI 的 D、DBQ、DCT、DCU、DDF、DGS、DGV 和 PW 表面貼裝封裝轉換為 100mil DIP 接頭。?????

用戶指南: PDF
TI.com 上無現貨
仿真模型

HSPICE Model for SN74CB3Q3306A

SCDJ017.ZIP (32 KB) - HSpice Model
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仿真模型

SN74CB3Q3306A IBIS Model

SCDM030.ZIP (25 KB) - IBIS Model
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參考設計

TIDEP0054 — 適用于變電站自動化的并行冗余協議 (PRP) 以太網參考設計

此參考設計為智能電網輸電和配電網絡中的變電站自動化設備提供高可靠性、低延遲網絡通信。它支持 IEC 62439 標準中使用 PRU-ICSS 的并行冗余協議 (PRP) 規范。此參考設計是 FPGA 方法的較低成本替代方法，可提供在無需額外組件的情況下添加 IEC 61850 支持等功能的靈活性和性能。
設計指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
TSSOP (PW) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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