SN74AVC20T245

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具有可配置電壓轉(zhuǎn)換和 3 態(tài)輸出的 20 位雙電源總線收發(fā)器

產(chǎn)品詳情

Bits (#) 20 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.065 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 20 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.065 Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm2 14 x 8.1 TVSOP (DGV) 56 72.32 mm2 11.3 x 6.4
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6-V Tolerant
  • Max Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 260 Mbps (1.8-V to 3.3-V Translation)
    • 260 Mbps (Translate to 2.5 V)
    • 210 Mbps (Translate to 1.8 V)
    • 120 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6-V Tolerant
  • Max Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 260 Mbps (1.8-V to 3.3-V Translation)
    • 260 Mbps (Translate to 2.5 V)
    • 210 Mbps (Translate to 1.8 V)
    • 120 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 20-bit noninverting bus transceiver uses two separate configurable power-supply rails.

The SN74AVC20T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC20T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so that the buses are effectively isolated.

The SN74AVC20T245 is designed so that the control (1DIR, 2DIR, 1OE\, and 2OE\) inputs are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 20-bit noninverting bus transceiver uses two separate configurable power-supply rails.

The SN74AVC20T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC20T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so that the buses are effectively isolated.

The SN74AVC20T245 is designed so that the control (1DIR, 2DIR, 1OE\, and 2OE\) inputs are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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仿真模型

HSPICE MODEL OF SN74AVC20T245

SCEJ164.ZIP (126 KB) - HSpice Model
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仿真模型

SN74AVC20T245 IBIS Model (Rev. A)

SCEM429A.ZIP (69 KB) - IBIS Model
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TSSOP (DGG) 56 Ultra Librarian
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