數(shù)據(jù)表
SN74AUC17
- Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub-1-V Operable
- Max tpd of 1.8 ns at 1.8 V
- Low Power Consumption, 10-μA Max ICC
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
This hex Schmitt-trigger buffer is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC17 contains six independent buffers and performs the Boolean function Y = A. The device functions as six independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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評估板
14-24-NL-LOGIC-EVM — 采用 14 引腳至 24 引腳無引線封裝的邏輯產(chǎn)品通用評估模塊
14-24-EVM 是一款靈活的評估模塊 (EVM),旨在支持具有 14 引腳至 24 引腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的任何邏輯或轉(zhuǎn)換器件。
參考設計
TIDA-00106 — 16 位 1MSPS 數(shù)據(jù)采集參考設計:具備隔離功能,可實現(xiàn)高壓共模抑制
該電路是一款高性能數(shù)據(jù)采集 (DAQ) 解決方案,適用于處理疊加在大共模偏移量(在直流至約 15kHz 頻率范圍內(nèi),測試共模偏移量最高達 155V 峰峰值)上的輸入信號(最高 ±12V),此處共模偏移量以系統(tǒng)主電源的地電位為基準。共模抑制通過生成隔離電源實現(xiàn),使模擬信號鏈可隨輸入共模信號浮動。模擬信號鏈包含一款高性能 16 位 1MSPS SAR ADC,該 ADC 具有集成模擬前端 (AFE),提供高輸入阻抗和 ±12V 寬輸入電壓范圍。相關(guān)應用領(lǐng)域包括帶通道間隔離的 PLC 模擬輸入模塊、汽車電池組監(jiān)控、交流電機驅(qū)動器中的功率監(jiān)控以及熱電偶測量。
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| VQFN (RGY) | 14 | Ultra Librarian |
訂購和質(zhì)量
包含信息:
- RoHS
- REACH
- 器件標識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
包含信息:
- 制造廠地點
- 封裝廠地點