產品詳情

Bits (#) 16 Data rate (max) (Mbps) 300 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 2.5 Vin (max) (V) 3.3 Vout (min) (V) 3.3 Vout (max) (V) 5 Applications GPIO Features Output enable, Very high speed Technology family ALVC Supply current (max) (mA) 0.04 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 16 Data rate (max) (Mbps) 300 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 2.5 Vin (max) (V) 3.3 Vout (min) (V) 3.3 Vout (max) (V) 5 Applications GPIO Features Output enable, Very high speed Technology family ALVC Supply current (max) (mA) 0.04 Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm2 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm2 12.5 x 8.1
  • Member of the Texas Instruments Widebus? Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners
  • Member of the Texas Instruments Widebus? Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
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* 數據表 SN74ALVC164245 16-Bit 2.5-V to 3.3-V or 3.3-V to 5-V Level-Shifting Transceiver With 3-State Outputs 數據表 (Rev. Q) PDF | HTML 2016年 9月 27日
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選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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應用手冊 Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
應用手冊 TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
應用手冊 Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
應用手冊 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
應用手冊 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
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選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發

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仿真模型

SN74ALVC164245 IBIS Model (Rev. C)

SCEM026C.ZIP (58 KB) - IBIS Model
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SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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