產品詳情

Technology family AHCT Number of channels 1 Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Supply current (max) (μA) 40
Technology family AHCT Number of channels 1 Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Supply current (max) (μA) 40
SOIC (D) 16 59.4 mm2 9.9 x 6 TSSOP (PW) 16 32 mm2 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • EPIC? (Enhanced-Performance Implanted CMOS) Process
  • Inputs Are TTL-Voltage Compatible
  • Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

EPIC is a trademark of Texas Instruments.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • EPIC? (Enhanced-Performance Implanted CMOS) Process
  • Inputs Are TTL-Voltage Compatible
  • Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

EPIC is a trademark of Texas Instruments.

The SN74AHCT138 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN74AHCT138 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
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類型 標題 下載最新的英語版本 日期
* 數據表 SN74AHCT138-EP 數據表 2003年 5月 2日
* VID SN74AHCT138-EP VID V6203655 2016年 6月 21日
* 輻射與可靠性報告 SN74AHCT138MDREP Reliability Report 2013年 3月 22日
應用手冊 慢速或浮點 CMOS 輸入的影響 (Rev. E) PDF | HTML 英語版 (Rev.E) 2025年 3月 26日
選擇指南 Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應用手冊 How to Select Little Logic (Rev. A) 2016年 7月 26日
應用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
選擇指南 小尺寸邏輯器件指南 (Rev. E) 最新英語版本 (Rev.G) 2012年 7月 16日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應用手冊 選擇正確的電平轉換解決方案 (Rev. A) 英語版 (Rev.A) 2006年 3月 23日
產品概述 Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
應用手冊 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
應用手冊 Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 2002年 12月 2日
應用手冊 Texas Instruments Little Logic Application Report 2002年 11月 1日
應用手冊 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
設計指南 AHC/AHCT Designer's Guide February 2000 (Rev. D) 2000年 2月 24日
產品概述 Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 1998年 4月 1日
應用手冊 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
應用手冊 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應用手冊 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
應用手冊 Live Insertion 1996年 10月 1日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設計和開發

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封裝 引腳 CAD 符號、封裝和 3D 模型
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓

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